Indicate in the table below if the instruction memory, data memory, or the immediate generation (sign-extend) unit are active for the given instructions. If the element is active for the given instruction, put an ‘X’ in the corresponding field. If not, leave the field blank.
Homework Answers
All variables, tables, stack etc are stored in data memory & all instructions (along with any literal constants that are part of instruction) are stored in instruction memory.
|
Instruction |
Instruction Memory |
Data Memory |
Immgen/Sign-extended |
|
addi |
X |
X |
|
|
sub |
X |
X |
X |
|
ld |
X |
X |
|
|
sd |
X |
X |
|
|
beq |
X |
X |
Add Answer to:
Indicate in the table below if the instruction memory, data
memory, or the immediate generation (sign-extend)...
Using the register and data memory contents listed in the table below, after executing the instruction:...
Using the register and data memory contents listed in the table
below, after executing the instruction:
mov.b WREG,
0x1001
What are the contents of 0x1000?
Using the register and data memory contents listed in the table
in Q7, after executing the instruction:
mov #0x1001, W0
What are the contents of 0x1000?
7. Using the register and data memory contents listed in the table below, after executing the instruction: mov.b WREG, Ox1001 What are the contents of Ox1000? ANSWER: Data Memory...
can you show me how you get each one or fill the table? Given the following memory and register values as shown in Tables 1& 2 below: Determine the values of the A, B, X, Y, CCR & SP regis...
can you show me how you get each one or fill the table?
Given the following memory and register values as shown in Tables 1& 2 below: Determine the values of the A, B, X, Y, CCR & SP registers in Table 1 as the program is executed Show new values of memory content in Table 2 if the memory location content is affected. - NOTE: This is a continues program where instruction results affect the instruction that follows Leave...
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides...
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides the percentage of executed instructions for each type of instruction. Instruction Executed P ipeline CPU type instructions (%) w/o hazards ALU 29.4 Load 29.7 Store 14.7 Branch 26.2 2 (w/o prediction) 27% of the load instructions are followed by instructions that need the data being loaded, 47% of the branches are actually.not taken, please assume not taken prediction. a) Please determine the overall cycles...
The datapath for 5-stage MIPS pipelined architecture is given below. IF/D ID/EX EX/MEM MEM/WB >Add Add...
The datapath for 5-stage MIPS pipelined architecture is given below. IF/D ID/EX EX/MEM MEM/WB >Add Add Add result Shift left 2 Address Instruction memory Read Read register 1 data Read register "Registers Read Write data 2 register Write data SALU ALU result Address Read data Data memory Write data 16 Sign- 32 extend Choose all the components that generate a useful result during the execution of the following instruction: Choose all the components that generate a useful result during the...
3. Assume the processor data path show below. XE30 Add Add ALU result Shift left 2...
3. Assume the processor data path show below. XE30 Add Add ALU result Shift left 2 RegDst Branch MemRead Instruction (31-26] RegSrc Control ALUOP Mem Write ALUSrc RegWrite PC Instruction (25-21) Read address Instruction (20-16] Instruction [31-0) Instruction instruction (15-11) memory Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers Zero ALU ALU result Read Address data OX OX3) 3x) Write Data data memory Instruction [15-0) 16 32 Sign- extend ALU control...
4. List the values on the control signals for the following instructions. The MIPS architecture and...
4. List the values on the control signals for the following instructions. The MIPS architecture and instruction formats studied in class are shown below for reference. Your answer needs to be 1, 0, or X for each signal (a 0 or 1 will not be accepted as a substitute for X) MemtoReg MemWriteBranchALUSrc RegDst RegWrite sub r2, r5, r23 beq rl, r3, L2 sw rl, 36(r4) lw r3,100(r6) addi r2,rl4,-24 j L3 ontro Unit Write ranch PCSrc Op Funct LUSre...
5 Exercises Now that everything is working you can try the following exercises. To complete them you will need to refer...
5 Exercises Now that everything is working you can try the following exercises. To complete them you will need to refer to the documentation in Appendix A- The MiteASM Assembler and Appendix B - The MiteFPGA Processor. Write an assembly language program for an over counter for a cricket umpire. This should display a count on the 7-segment display. The count should increase by 1 when button 0 is 1. pressed. It should reset to 0 when button 1 is...
There is an example below Now that everything is working you can try the following exercises. To complete them you wi...
There is an example below
Now that everything is working you can try the following exercises. To complete them you will need to refer to the documentation in Appendix A The MiteASM Assembler and Appendix B The MiteFPGA Processor. Write an assembly language program for an over counter for a cricket umpire. This should 1. display a count on the 7-segment display. The count should increase by 1 when button 0 is pressed. It should reset to 0 when button...
T F Xilinx's SDK assembler supports both FOR statements, but not wHILE statements T F In the ARM processor, immediate operands are stored in data memory, and not in the opcode T F In ARM proc...
T F Xilinx's SDK assembler supports both FOR statements, but not wHILE statements T F In the ARM processor, immediate operands are stored in data memory, and not in the opcode T F In ARM processor instructions, one but not both operands can come from main T F In the ARM processor, a single load/store instruction T F It is possible for a microprocessor to use a virtual TCache memory is typically much faster and much larger than main memory...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
Using the register and data memory contents listed in the table
below, after executing the instruction:
mov.b WREG,
0x1001
What are the contents of 0x1000?
Using the register and data memory contents listed in the table
in Q7, after executing the instruction:
mov #0x1001, W0
What are the contents of 0x1000?
7. Using the register and data memory contents listed in the table below, after executing the instruction: mov.b WREG, Ox1001 What are the contents of Ox1000? ANSWER: Data Memory...
can you show me how you get each one or fill the table?
Given the following memory and register values as shown in Tables 1& 2 below: Determine the values of the A, B, X, Y, CCR & SP registers in Table 1 as the program is executed Show new values of memory content in Table 2 if the memory location content is affected. - NOTE: This is a continues program where instruction results affect the instruction that follows Leave...
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides the percentage of executed instructions for each type of instruction. Instruction Executed P ipeline CPU type instructions (%) w/o hazards ALU 29.4 Load 29.7 Store 14.7 Branch 26.2 2 (w/o prediction) 27% of the load instructions are followed by instructions that need the data being loaded, 47% of the branches are actually.not taken, please assume not taken prediction. a) Please determine the overall cycles...
The datapath for 5-stage MIPS pipelined architecture is given below. IF/D ID/EX EX/MEM MEM/WB >Add Add Add result Shift left 2 Address Instruction memory Read Read register 1 data Read register "Registers Read Write data 2 register Write data SALU ALU result Address Read data Data memory Write data 16 Sign- 32 extend Choose all the components that generate a useful result during the execution of the following instruction: Choose all the components that generate a useful result during the...
3. Assume the processor data path show below. XE30 Add Add ALU result Shift left 2 RegDst Branch MemRead Instruction (31-26] RegSrc Control ALUOP Mem Write ALUSrc RegWrite PC Instruction (25-21) Read address Instruction (20-16] Instruction [31-0) Instruction instruction (15-11) memory Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers Zero ALU ALU result Read Address data OX OX3) 3x) Write Data data memory Instruction [15-0) 16 32 Sign- extend ALU control...
4. List the values on the control signals for the following instructions. The MIPS architecture and instruction formats studied in class are shown below for reference. Your answer needs to be 1, 0, or X for each signal (a 0 or 1 will not be accepted as a substitute for X) MemtoReg MemWriteBranchALUSrc RegDst RegWrite sub r2, r5, r23 beq rl, r3, L2 sw rl, 36(r4) lw r3,100(r6) addi r2,rl4,-24 j L3 ontro Unit Write ranch PCSrc Op Funct LUSre...
5 Exercises Now that everything is working you can try the following exercises. To complete them you will need to refer to the documentation in Appendix A- The MiteASM Assembler and Appendix B - The MiteFPGA Processor. Write an assembly language program for an over counter for a cricket umpire. This should display a count on the 7-segment display. The count should increase by 1 when button 0 is 1. pressed. It should reset to 0 when button 1 is...
There is an example below
Now that everything is working you can try the following exercises. To complete them you will need to refer to the documentation in Appendix A The MiteASM Assembler and Appendix B The MiteFPGA Processor. Write an assembly language program for an over counter for a cricket umpire. This should 1. display a count on the 7-segment display. The count should increase by 1 when button 0 is pressed. It should reset to 0 when button...
T F Xilinx's SDK assembler supports both FOR statements, but not wHILE statements T F In the ARM processor, immediate operands are stored in data memory, and not in the opcode T F In ARM processor instructions, one but not both operands can come from main T F In the ARM processor, a single load/store instruction T F It is possible for a microprocessor to use a virtual TCache memory is typically much faster and much larger than main memory...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
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