HomeworkLib
Question

Given an i-cache using direct mapping with 32 lines and a block size of 16, what...

Given an i-cache using direct mapping with 32 lines and a block size of 16, what are the tag, index, and offset of the reference word 0x123456? What if the cache is 16 lines?

engineering   Computer-Science   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

Given incache number of cache lines = 32 index = logo (cache lines) =1092120) index = 5 bits Block size = 16 offeer = log2 (b1 2 3 4 5 6 0001 0010 00110100 0101 to the referenced word (is binary) ပ၀၀၊ ဝolo oo O၂ဝဝ ဝ၅၄၄ - index offier (4 bits) yag a5:. Топ = jь bik index= 4 bits offer a 4 bits

0 0
Add a comment
Know the answer?
Add Answer to:
Given an i-cache using direct mapping with 32 lines and a block size of 16, what...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • For a 16K-byte, direct-mapped cache, suppose the block size is 32 bytes, draw a cache diagram....

    For a 16K-byte, direct-mapped cache, suppose the block size is 32 bytes, draw a cache diagram. Indicate the block size, number of blocks, and address field decomposition (block offset, index, and tag bit width) assuming a 32-bit memory address.

  • Consider a system with 24 bit addresses, 128 KB cache with 32 byte lines using direct...

    Consider a system with 24 bit addresses, 128 KB cache with 32 byte lines using direct mapping. Divide the address below labeling each part of the address and specify the size of each field in bits. Tag? Line? Offset?

  • Given a 32-bit address, calculate the following values for a two-way set associative for: Cache size:...

    Given a 32-bit address, calculate the following values for a two-way set associative for: Cache size: 32KB Block size: 64B i) The number of bits in the block offset field. ii) The number of index bits. iii) The number of sets in the cache. iv) The number of tag bits.

  • Cache Layout: A processor has a separate D-cache and an I-cache. D-cache: 64KB, 4-way set associative,...

    Cache Layout: A processor has a separate D-cache and an I-cache. D-cache: 64KB, 4-way set associative, block size of 1 word, write-back policy I-cache: 32KB, direct mapped cache, block size of 1 word The processor uses the LRU algorithm for its replacement policy. Answer the following questions. Make sure that you account for all the book -keeping bits. A word is 4 bytes (a) Calculate the number of tag, index and offset bits for the D-cache. (b) Calculate the number...

  • Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a...

    Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...

  • question 2 and 3 2. Determine how many sets of cache blocks will be there for...

    question 2 and 3 2. Determine how many sets of cache blocks will be there for the following Cache memory size (in bytes) Direct Mapped Blocks Size (in bits) 32 64 218 2-way Set Associative Block Size (in bits) 32 64 A 2A6 [0.5 * 16 = 8] 4-way Set Associative Block Size (in bits) 32 64 SK 64K 256K 3. The physical memory address generated by a CPU is converted into cache memory addressing scheme using the following mapping...

  • For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits are...

    For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits are used to access the cache. TAG INDEX OFFSET 31-15 14-8 7-0 a. What is the cache block size (in words)? [13 points] b. How many blocks does the cache have? [12 points]

  • Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of...

    Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of cache, and a block size of 16 bytes. For each configuration below, determine the memory address format, indicating the number of bits needed for each appropriate field (i.e. tag, block, set, offset). Show any relevant calculations. Direct cache mapping and memory is byte-addressable a) Direct cache mapping and memory is word-addressable with a word size of 16 bits b) c) 2-way set associative cache...

  • A 256kiB (2^18 bytes) cache has a block size of 32 bytes and is 32-way set-associative....

    A 256kiB (2^18 bytes) cache has a block size of 32 bytes and is 32-way set-associative. How many bits of a 32-bit address will be in the Tag, Index, and Bock Offset?

  • Please refer the following memory system : Main memory : 64 MB Cache memory: 64 KB...

    Please refer the following memory system : Main memory : 64 MB Cache memory: 64 KB Block size of 1 KB 1. Direct Mapping Offset bits? Number of lines in cache? Line number bits? Tag size? 2. Fully Associative Mapping Offset bits? Tag size? 3. 2-way set-associative mapping Offset bits? Number of lines in cache? Set number bits? Tag size? 4. 4-way set-associative mapping Offset bits? Number of lines in cache? Set number bits? Tag size?

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT