HomeworkLib
Question

Modify the Moore FSM below to detect the sequence "110" , simulate using the same test...

Modify the Moore FSM below to detect the sequence "110" , simulate using the same test bench and create a Moore Transition Diagram for the new sequence 110.

module moore_seq
(
   input clock, reset, x,
   output reg z
);
//assign binary encoded codes to the states A through D
parameter
   A = 2'b00,
   B = 2'b01,
   C = 2'b10,
   D = 2'b11;
reg [1 : 0] current_state, next_state;

//Section 1: Next state generator (NSG)
always@(*)
begin
   casex (current_state)

   A: if ( x == 1)
       next_state = B;

   else

       next_state = A;

   B: if (x ==1)
       next_state = B;

   else

       next_state = C;

   C: if (x == 1)
       next_state = D;

   else

       next_state = A;

   D: if (x == 1)
       next_state = B;

   else

       next_state = C;

   endcase
end

//Section 2: Output generator
always@(*)
begin
   if (current_state == D)
       z = 1;
   else
       z = 0;
end


//Section 3: The Flip-flops
always@(posedge clock, posedge reset)
begin
   if (reset == 1)
       current_state <= A;

   else

       current_state <= next_state;
   end

endmodule

// This the test bench

`include "moore_seq.v"

module moore_seq_tb();

reg clock, reset, x;

wire z;

moore_seq u1(clock, reset, x, z);


initial begin
$monitor("%4d: z = %b", $time, z);
clock = 0;
reset = 1;
x = 0;
#10 reset = 0;
end


always begin
#5clock = ~clock;
end

initial begin

#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 0; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 0; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x= 1; $display("%4d: x = %b", $time, x);
#10 x = 0; $display("%4d: x = %b", $time, x);
#10 x= 0; $display("%4d: x = %b", $time, x);
#10 $finish;
end
endmodule

  

engineering   Computer-Science   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

CHANGED DESIGN MODULE:-

module moore_seq

(

input clock, reset, x,

output reg z

);

//assign binary encoded codes to the states A through D

parameter

A = 2'b00,

B = 2'b01,

C = 2'b10,

D = 2'b11;

reg [1 : 0] current_state, next_state;

//Section 1: Next state generator (NSG)

always@(*)

begin

casex (current_state)

A: if ( x == 1)

next_state = B;

else

next_state = A;

B: if (x ==1)

next_state = C;

else

next_state = A;

C: if (x == 1)

next_state = C;

else

next_state = D;

D: if (x == 1)

next_state = B;

else

next_state = A;

endcase

end

//Section 2: Output generator

always@(*)

begin

if (current_state == D)

z = 1;

else

z = 0;

end

//Section 3: The Flip-flops

always@(posedge clock, posedge reset)

begin

if (reset == 1)

current_state <= A;

else

current_state <= next_state;

end

endmodule

output screenshot:-

0 0
Add a comment
Know the answer?
Add Answer to:
Modify the Moore FSM below to detect the sequence "110" , simulate using the same test...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code...

    Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code Simulate the circuit using ISim and analyze the resulting waveform. Verilog Code for dff_fe_asyn_h is mentioned below:- //DFF module with asynchronous active high reset with negative edge trigger with clock module dff_fe_asyn_h ( input clock, // Clock Input input reset, // Reset Input input data_in, // Input Data output reg data_out // Output Data ); always @ (negedge clock or posedge reset) // triggers...

  • Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code...

    Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code Simulate the circuit using ISim and analyze the resulting waveform. Take full screenshots of all Verilog source codes and the resulting simulation waveform to be included in the lab report. Include explanation of the waveform and how you can conclude that the D flip flop implemented in step 9 is correct in the lab report. Verilog Code for dff_fe_asyn_h is mentioned below:- //DFF module...

  • Im building a clock using HDL system verilog and I need help implementing this instantiation meth...

    Im building a clock using HDL system verilog and I need help implementing this instantiation method. Basically what happens is in the top module ClockCounter, positive clock edges are counted and passed into module timer using instantiation. Once the counter reaches MaxCount (59), a carry is generated which increments the minute clock. Once the minute clock reaches 59, another carry is generated which increments the hour clock. In module timer() below, I need help figuring out what variables in each...

  • Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset,...

    Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset, clk, TB, TA, output reg [1:0] LB, LA); reg [1:0] cstate, nstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; parameter grn = 2'b00; parameter ylw = 2'b01; parameter rd = 2'b10; // state register always @ (posedge clk, posedge reset) begin if (reset) cstate <= S0; else cstate <= nstate; end // next state logic...

  • Could you help me understand what happening in this function, also adjust it to have a  period...

    Could you help me understand what happening in this function, also adjust it to have a  period of 2 seconds and duty cycle 50% module complexDivider (clk50Mhz, slowclk) input clk50Mhz;//fast clock output slowClk;1/slow clock reg [26:01 counter; initial begin counter0; end always (posedge clk50Mhz) begin if (counter == 25000000) begin counter <= 1; end else begin counter <= counter + 1; end end endmodule

  • I need help writing the Verilog Design code for this test bench. I have to calculate...

    I need help writing the Verilog Design code for this test bench. I have to calculate the dot product of two 8-bit vectors a and b. I have listed the test bench below: // Code your testbench here module test_VVM; wire [3:0] value; wire done; reg clk, rst; reg [7:0] a, b; initial begin a = 8'b11011101; b = 8'b11010111;    clk = 1'd0;   //at time 0    rst = 1'd0; //at time 0    rst = #2 1'd1; //at...

  • 3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left,...

    3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q; input [7:0] Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<= Data_in; else case ( { Shift_left, Shift_right }) 2'600: if (Clk == 1) Q<=Q; 2'b01: if (Clk == 1) Q<= >> 1; 2'b10: if (Clk == 1) Q<=Q<< 1; default: Q<=Q; endcase endmodule a) What does reg (7:0] Q do? b)...

  • I need help writing a test bench for the following Verilog code module CU(IE, WE, WA,...

    I need help writing a test bench for the following Verilog code module CU(IE, WE, WA, RAE, RAA, RBE, RBA, ALU,                SH, OE, start, clk, reset, Ng5); //nG5 denotes (N>5);    input start, clk, reset;    output IE, WE, RAE, RBE, OE;    output [1:0] WA, RAA, RBA, SH;    output [2:0] ALU;       input wire Ng5;    reg [1:0] state;    reg [1:0] nextstate;    parameter S0 = 3'b000;    parameter S1 = 3'b001;...

  • (15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR,...

    (15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule

  • Answer the question below for the following code, What does reg (7:0) do? What does always...

    Answer the question below for the following code, What does reg (7:0) do? What does always @ (posedge Cik) do? C What causes 2"b01: if (Clk 1) Q<= >> 1 to execute? When it executes, what does it do module Shift_Register (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q, input (7:0) Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<Data_in; else case ( { Shift_left, Shift_right)) 2'600: if (Clk - 1)...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT