Question

Why does a task statement not require inputs, but function statement, module template and system task do?

What is the difference between task and system task?\

Can high fanouts cause a time constraint?

Answer 1

1a)

Tasks are used in all programming languages, generally known as procedures or subroutines. The lines of code are enclosed in task....end task brackets. Data is passed to the task, the processing done, and the result returned. They have to be specifically called, with data ins and outs, rather than just wired in to the general netlist. Included in the main body of code, they can be called many times, reducing code repetition.
		tasks are defined in the module in which they are used. It is possible to define a task in a separate file and use the compile directive 'include to include the task in the file which instantiates the task. tasks can include timing delays, like posedge, negedge, # delay and wait. tasks can have any number of inputs and outputs. The variables declared within the task are local to that task. The order of declaration within the task defines how the variables passed to the task by the caller are used. tasks can take, drive and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of task execution. tasks can call another task or function. tasks can be used for modeling both combinational and sequential logic. A task must be specifically called with a statement, it cannot be used within an expression as a function can.
	$../images/main/bulllet_4dots_orange.gif$	Syntax
		A task begins with keyword task and ends with keyword endtask Inputs and outputs are declared after the keyword task. Local variables are declared after input and output declaration.
	$../images/main/bulllet_4dots_orange.gif$	Example - Simple Task
		1 module simple_task(); 2 3 task convert; 4 input [7:0] temp_in; 5 output [7:0] temp_out; 6 begin 7 temp_out = (9/5) *( temp_in + 32) 8 end 9 endtask 10 11 endmodule You could download file simple_task.v here
	$../images/main/bulllet_4dots_orange.gif$	Example - Task using Global Variables
		1 module task_global(); 2 3 reg [7:0] temp_out; 4 reg [7:0] temp_in; 5 6 task convert; 7 begin 8 temp_out = (9/5) *( temp_in + 32); 9 end 10 endtask 11 12 endmodule You could download file task_global.v here
	$../images/main/bulllet_4dots_orange.gif$	Calling a Task
		Let's assume that the task in example 1 is stored in a file called mytask.v. Advantage of coding a task in a separate file, is that it can be used in multiple modules.
		1 module task_calling (temp_a, temp_b, temp_c, temp_d); 2 input [7:0] temp_a, temp_c; 3 output [7:0] temp_b, temp_d; 4 reg [7:0] temp_b, temp_d; 5 `include "mytask.v" 6 7 always @ (temp_a) 8 begin 9 convert (temp_a, temp_b); 10 end 11 12 always @ (temp_c) 13 begin 14 convert (temp_c, temp_d); 15 end 16 17 endmodule You could download file task_calling.v here
	$../images/main/bulllet_4dots_orange.gif$	Example - CPU Write / Read Task
		Below is the waveform used for writing into memory and reading from memory. We make the assumption that there is a need to use this interface from multiple agents. So we write the read/write as tasks.
		$../images/verilog/task_cpu_wr_rd.gif$
		1 module bus_wr_rd_task(); 2 3 reg clk,rd,wr,ce; 4 reg [7:0] addr,data_wr,data_rd; 5 reg [7:0] read_data; 6 7 initial begin 8 clk = 0; 9 read_data = 0; 10 rd = 0; 11 wr = 0; 12 ce = 0; 13 addr = 0; 14 data_wr = 0; 15 data_rd = 0; 16 // Call the write and read tasks here 17 #1 cpu_write(8'h11,8'hAA); 18 #1 cpu_read(8'h11,read_data); 19 #1 cpu_write(8'h12,8'hAB); 20 #1 cpu_read(8'h12,read_data); 21 #1 cpu_write(8'h13,8'h0A); 22 #1 cpu_read(8'h13,read_data); 23 #100 $finish; 24 end 25 // Clock Generator 26 always 27 #1 clk = ~clk; 28 // CPU Read Task 29 task cpu_read; 30 input [7:0] address; 31 output [7:0] data; 32 begin 33 $display ("%g CPU Read task with address : %h", $time, address); 34 $display ("%g -> Driving CE, RD and ADDRESS on to bus", $time); 35 @ (posedge clk); 36 addr = address; 37 ce = 1; 38 rd = 1; 39 @ (negedge clk); 40 data = data_rd; 41 @ (posedge clk); 42 addr = 0; 43 ce = 0; 44 rd = 0; 45 $display ("%g CPU Read data : %h", $time, data); 46 $display ("======================"); 47 end 48 endtask 49 // CU Write Task 50 task cpu_write; 51 input [7:0] address; 52 input [7:0] data; 53 begin 54 $display ("%g CPU Write task with address : %h Data : %h", 55 $time, address,data); 56 $display ("%g -> Driving CE, WR, WR data and ADDRESS on to bus", 57 $time); 58 @ (posedge clk); 59 addr = address; 60 ce = 1; 61 wr = 1; 62 data_wr = data; 63 @ (posedge clk); 64 addr = 0; 65 ce = 0; 66 wr = 0; 67 $display ("======================"); 68 end 69 endtask 70 71 // Memory model for checking tasks 72 reg [7:0] mem [0:255]; 73 74 always @ (addr or ce or rd or wr or data_wr) 75 if (ce) begin 76 if (wr) begin 77 mem[addr] = data_wr; 78 end 79 if (rd) begin 80 data_rd = mem[addr]; 81 end 82 end 83 84 endmodule You could download file bus_wr_rd_task.v here
		Simulation Output
		1 CPU Write task with address : 11 Data : aa 1 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 4 CPU Read task with address : 11 4 -> Driving CE, RD and ADDRESS on to bus 7 CPU Read data : aa ====================== 8 CPU Write task with address : 12 Data : ab 8 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 12 CPU Read task with address : 12 12 -> Driving CE, RD and ADDRESS on to bus 15 CPU Read data : ab ====================== 16 CPU Write task with address : 13 Data : 0a 16 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 20 CPU Read task with address : 13 20 -> Driving CE, RD and ADDRESS on to bus 23 CPU Read data : 0a ======================
	$../images/main/bullet_green_ball.gif$	Function
		A Verilog HDL function is the same as a task, with very little differences, like function cannot drive more than one output, can not contain delays.
		functions are defined in the module in which they are used. It is possible to define functions in separate files and use compile directive 'include to include the function in the file which instantiates the task. functions can not include timing delays, like posedge, negedge, # delay, which means that functions should be executed in "zero" time delay. functions can have any number of inputs but only one output. The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the caller are used. functions can take, drive, and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of function execution. functions can be used for modeling combinational logic. functions can call other functions, but can not call tasks.
	$../images/main/bulllet_4dots_orange.gif$	Syntax
		A function begins with keyword function and ends with keyword endfunction inputs are declared after the keyword function.
	$../images/main/bulllet_4dots_orange.gif$	Example - Simple Function
		1 module simple_function(); 2 3 function myfunction; 4 input a, b, c, d; 5 begin 6 myfunction = ((a+b) + (c-d)); 7 end 8 endfunction 9 10 endmodule You could download file simple_function.v here
	$../images/main/bulllet_4dots_orange.gif$	Example - Calling a Function
		1 module function_calling(a, b, c, d, e, f); 2 3 input a, b, c, d, e ; 4 output f; 5 wire f; 6 `include "myfunction.v" 7 8 assign f = (myfunction (a,b,c,d)) ? e :0; 9 10 endmodule