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4701 10:38 ← tutorials.pdf a스 Sohar Usiversity COMPLL3 Fundamental of Computer Syshens ALU

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1 answer:

CPU Special Registers

The CPU contains a number of special-purpose registers:

Instruction Register (IR): The instruction register holds the instruction currently being executed.

Memory Data Register (MDR): The memory data register (also known as the memory buffer register or data buffer) holds the piece of data that has been fetched from memory.

Memory Address Register (MAR): The memory address register holds the address of the next piece of memory to be fetched.

Program Counter (PC): The program counter holds the location of the next instruction to be fetched from memory. It is automatically incremented between supplying the address of the next instruction and the instruction being executed.

Accumulator: The accumulator is an internal CPU register used as the default location to store any calculations performed by the arithmetic and logic unit.

Next: General Purpose Registers

2 answer:

Instruction address Inucoon Fetch Program Counter Fu ack Increment Unit PCU ack New PC Feeched Deta ALU req ALU ack Arithmetc

3 answer:

We begin with truth tables for the sum and carry-out bits produced when two binary numbers are added together with a carry-in. First we will look at the sum expression. given two input bits and a carry-in, we have three variables and need a truth table with eight rows to represent all possible combinations of three binary variables.

After adding all combinations we see that the sum should be 1 whenever the combination of inputs is odd. This is an odd function, which could easily be represented by exclusive-or gates. But or goal here is to practice with truth tables, disjunctive normal form, karnaugh maps and designing digital circuits. So we begin by developing the disjunctive normal form for the following truth table representing the sum:

Binary One-bit
Full Adder Sum Table

x

y

Cin

Sum

0

0

0

0

0

0

1

1

x’y’Cin

0

1

0

1

x’yCin’

0

1

1

0

1

0

0

1

xy’Cin’

1

0

1

0

1

1

0

0

1

1

1

1

xyCin

Sum = x’y’Cin + x’yCin’ + xy’Cin’ + xyCin.

Now that we have determined the sum-of-products (disjunctive normal form) for the sum expression, we attempt to reduce this to a simpler expression requiring fewer gates to build. Here we will use the karnaugh map:

x \ y Cin

0 0

0 1

1 1

1 0

0

0

1

0

1

1

1

0

1

0

No simplification up to this point. So we move on to the carry-out expression.

The carry-out truth table represents a majority circuit, the output is high whenever the number of high inputs is greater than the number of low inputs. Again we determine the disjunctive normal form for the Cout expression:

Binary One-bit
Full Adder Cout Table

x

y

Cin

Cout

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

1

x’yCin

1

0

0

0

1

0

1

1

xy’Cin

1

1

0

1

xyCin’

1

1

1

1

xyCin

Cout = x’yCin + xy’Cin + xyCin’ + xyCin.
Using the karnaugh map we get:

x \ y Cin

0 0

0 1

1 1

1 0

0

0

0

1

0

1

0

1

1

1

We can make three blocks of two to get a reduced circuit:

Cout = xCin + xy + yCin.
We should take a moment to verify that this is indeed an equivalent circuit by ensuring that the truth table is the same for both.

x

y

Cin

xCin + xy + yCin

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

1

1

0

0

0

0

0

0

1

0

1

1

0

0

1

1

1

0

0

1

0

1

1

1

1

1

1

1

1

So this reduced circuit is the same. We combine the results into a single circuit with three inputs and two outputs to get the following drawing:

S ur Cout = xCǐn + xy+yCin in Cout

4 answer:

Full adder(Full Adder implementation) 3x8 m ! 이내 벼6 m了

Full Subtractor

-Difference 2 2 3-to-8 Decoder 4 2 8 Bin 0 2 Borrow Out Figure 8.30 Answer to problem 4

5 answer:

  • The device that is allowed to initiate data transfers on the bus at any given time is called the bus master. In a computer system there may be more than one bus master such as processor, DMA controller etc.
  • They share the system bus. When current master relinquishes control of the bus, another bus master can acquire the control of the bus.
  • Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. The selection of bus master is usually done on the priority basis.
  • There are two approaches to bus arbitration: Centralized and distributed.

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