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sequence to be detected 1100. Choose either JK flipflop or D flipflop Lab 3: State Machine...

sequence to be detected 1100. Choose either JK flipflop or D flipflop
Lab 3: State Machine Sequence Detector Introduction This lab will build on what you have learnt so far in this module on the

You must simulate your design in Logisim when completed. Your design procedure must make up part of your report, and in parti

Lab 3: State Machine Sequence Detector Introduction This lab will build on what you have learnt so far in this module on the topic of sequential circuit analysis and design. In the previous lab you have investigated combination logic. Today, we will focus on designing a sequential circuit for a sequence detector using edge-triggered D- type or JK-type flip-flops. We will use the concept of a finite state machine to design a circuit capable of detecting a specific pattern of bits in an arbitrary length serial bit sequence, as discussed in class. Design Specification You are required to work in pairs to design a 4-bit sequence detector which analyses an incoming serial data stream, and outputs a logic HIGH, for one clock cycle, when a specific sequence is detected. Overlapping sequences should not produce a logic HIGH output in this design exercise. The sequence to be detected is determined by the last two digits of the lead partner's student number, according to the table below the lead partner must be decided between you, and should be indicated on the report sheet provided by ticking the appropriate box). Sequence to be detected 0101 Second last digit even number even number odd number Last digit even number odd number even number odd number 0100 1100 odd number 1011 All sequences are left-hand started i.e. the leftmost number enters the sequence detector first. The detector must be able to detect the sequence above from every possible input stream that is contained within, and must not give any false positives. As an example sequence, try inputting: 01011 01110 01101 01010 01000. This contains all the 4-bit sequences tabulated above, so should give a logic HIGH output for one clock cycle on the last bit of the relevant sequence. Design Procedure and Report You are required to carry out your design using one of the following flip-flop types: a) JK flip-flops, or b) D flip-flops. There are two kinds of state machines: Moore machines and Mealy machines. In Moore machines, the output depends only on the current state stored inside the machine. In Mealy machines, the output depends on both the stored state and the current input. You need to decide which machine you choose to design for this detector. Or you may design both, compare them and explain the difference between them.
You must simulate your design in Logisim when completed. Your design procedure must make up part of your report, and in particular you should separate your report into the following sections, identifying each part by its corresponding number: 1. This section should contain a state diagram describing how the state machine should behave. All states should be labelled eg. A, B, C etc., and every state must have its next state explicitly shown depending on the circuit input(s), and an output should be given for cach state. 2. You should give a brief description of the meaning assigned to each state. 3. You should also include the state table, which can be determined directly from the state diagram in part 1. 4. Each state must then be assigned a unique binary code, and the number of flip-flops required should be determined at this stage. 5. For each flip-flop, you should find the input value(s) that are needed to send that flip-flop to the next state, and this must be done for every possible state the flip-flops can be in. This can be summarised in a table, showing the binary values of the current state and next state, and the flip-flop inputs. 6. You should then simplify these flip-flop input equations using whatever method you deem appropriate e.g. by use of Karnaugh maps. 7. Write down the output of your circuit for the following input bit sequence (repeated from above): 01011 01110 01101 01010 01000. Use a table to emphasise the timing, and show the state the circuit is in during cach bit. For example, a sequence detecter designed to find the bit pattern 1110 in the input given above, might generate the following table: Input bit 01011011100110101010 01000 Output bit 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State ABABC ABCDAA BCABABABAABAAA Note: bits get clocked into the state machine at the start of each column. 8. What are the advantages and disadvantages of the flip-flop type you have chosen to implement your design? Give one of each. 9. As mentioned, there are two kinds of state machines: Moore machine and Mealy machine. Which machine have you designed? Explain what is the main difference between them? If you have extra time, repeat the above steps for the other machine. 10. Ensure that a TA verifies your circuit, and signs the cover sheet, before you submit your report.
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