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Design and implement synchronous dual port 128×8 RAM using VHDL. Dual port RAM supports simultane...

Design and implement synchronous dual port 128×8 RAM using VHDL. Dual port RAM supports simultaneous read and write operations.

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sync_dual_port_ram is
   port (   clock    : in std_logic;
       port0_en: in std_logic;
       port1_en: in std_logic;
       rd_wr   : in std_logic;
       din0   : in std_logic_vector(7 downto 0);
       din1   : in std_logic_vector(7 downto 0);
       addr0   : in std_logic_vector(6 downto 0);
       addr1   : in std_logic_vector(6 downto 0);
       dout0   : out std_logic_vector(7 downto 0);
       dout1   : out std_logic_vector(7 downto 0)
   );
end sync_dual_port_ram;

architecture arch of sync_dual_port_ram is

type memory is array (0 to 127) of std_logic_vector(7 downto 0);
signal ram : memory;

begin

process(clock)
begin
   if rising_edge(clock) then
       if (rd_wr = '0') then
           if (port0_en = '1') then
               ram(conv_integer(addr0)) <= din0;
           end if;
           if (port1_en = '1') then
               ram(conv_integer(addr1)) <= din1;
           end if;
       else
       end if;
   end if;

end process;

process(clock)
begin
   if rising_edge(clock) then
       dout0 <= ram(conv_integer(addr0));
       dout1 <= ram(conv_integer(addr1));
   end if;
end process;

end arch;

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