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A CPU produces the following sequence of read addresses in hexadecimal: 54, 58, 104, 5C, 108, 60, F0, 64, 54, 58, 10C, 5C, 110, 60, F0, 64
Supposing that the cache is empty to begin with, and assuming an LRU replacement, determine whether each address produces a hit or a miss for each of the following caches: (a) direct mapped in Figure 1, (b) fully associative in Figure 2, (c) two-way set associative in Figure 3.
Figure 1 Direct Mapped Cache
Figure 2 Fully Associative Cache
Figure 3 Two-Way Set-Associative Cache
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