Question

8. Use Quartus 2 to detail the process of designing and simulating a circuit (including menu manipulation, etc.).

Answer 1

Step by step explanation of designing and simulating circuit using Quartus 2

Step 1

1. Go to file menu
2. Select ' New project wizard '
3. The dialogue box as shown below opens
   New Project Wizard: Directory, Name, and Top-Level Entity [page 1 of 6] What is the working directory for this project? This directory will contain design files and other related files associated with this project. If you type a directory name that does not exist, Quartus Il can create it for you. ettings waseem&My Documents\Waseem Teaching ECE 465\spring05%Demo_S05 What is the name of this project? If you wish, you can use the name of the project's top-level entity Demo_S05 What is the name of the top-level entity in your project? Entity names are case sensitive so the capitalization must exactly match that of the name of the entity in the file. Demo_S05 Back Next Finish Cancel
   
4. Fill all the above fields
5. 
   New Project Wizard: Add Files [page 2 of 6] Select the design files and software source files you want to include in your project. Click Add All to add all design files and software source files in the project directory Note: it is optional to add files here unless you have design files not contained in the project directory, or files in which the file name is not the same as the entity name. File name Туре Add.. Add All Remove Properties Up Down If your project includes libraries of custom functions, specify their pathnames: User Library Pathnames... Back Finish Cancel Next X
   In above screen add any previous projects if available, if not skip this
6. In screen 3 select any additional PLD tools to be added else skip
7. In screen 4 select the target device family
8. In screen 5 specify the list of devices, leave it as default
9. In screen 6 verify the data and click finish
   New Project Wizard: EDA Tool Settings [page 3 of 6] Specify the other EDA tools -in addition to the Quartus Il software- this project that you will use on EDA tools Tool type Design entry/synthesis Simulation Tool name <None> <None <None <None> <None> <None> Timing analysis Board-level Formal verification Resynthesis Tool settings Tool type Design entry/synthesis Tool name: <None> Run this tool automatically to synthesize the current design Settings Advanced Back Finish Cancel Next Screen3 New Project Wizard: Device Family [page 4 of 6] Which device family do you wish to target? Family Cyclone Do you want to assign a specific device? C Yes No. I want to allow the Compiler to choose a device Cancel Back Next Finish Screen4
   
   New Project Wizard: Select an Auto Device [page 5 of 6] X Use the Fiters settings to control the devices that the Compiler can use when it selects a device, then click Next to continue. Available devices for the Compiler to target EP1C3T100C6 EP1C3T144C6 EP1C4F324C6 Filters Any Package: Any Eicer400 EP1C60240C6 EP1C6T144C6 EP1C12F256C6 EP1C12F324C6 Pin count Speed grade: Fastest Voltage: n/a EPIC20E324CE EP1C20F400C6 Back Next Firish Cancel Screen5 ew Project Wizard: Summary [page 6 of 6] When you click Finish, your project will be created with the following settings: Project directory: c:/documents and settings/waseem/my Demo S05 Demo S05 Project name: Top-level design entity Number of files added 0 Number of user libraries added 0 EDA tools: Design entry/synthesis: <None> Simulation <None> Timing analysis: <None> Board design <None> Device assignments: Family name: Cyclone Device: AUTO Finish Cancel Back Next Screen6
   
10. Now we finished creating the project space, now create the design files for our project. Block diagram/schematic based design is the easiest. So we follow that.
11. To create new design, Go to file menu -> New
    New Device Design Files Software Files Other Files AHDL File Block Diagram/Schematic File EDIF File Verilog HDL File VHDL File Cancel OK X
    
12. Click block diagram/schematic file and press ok. A new schematic editor opens. The symbol tool ( shape of and gate ) have all the logic elements we need frequently. We simply select that element using ‘Symbol Tool’ and place it on the schematic file by the click of mouse and keep on clicking till we have placed it for the required number of times. When we are done, we just press ‘ESC’ key and the mouse pointer returns to the normal arrow pointer. The below figures shows them.
    Cancel AOFFrrreD poooo0 2LL
    
    Libraries or2 or3 her L output storage Nam nput Repeat inert mode Imert senbg o block unch Meawirad gin Megswiead Plugin Manager OK Cancel Symbol Lbrarin nands nndi nor12 Repeatinont wode Megawiraid Pgin Manage OK Cancel SYmbe Lbaries others pintives other LO hid HO torage ANY a 4 Name oulpul Regealnoert mode Ener auntil e bock rLaunchiMepicd P MegaWd Plugin Manager Cancel
    
13. Place all the elements as per the circuit and connect them.
14. Now save the schematic, while saving make sure that ' Add file to current project ' is ticked
    Save As Demo_S05 Save in: |db Demo_S05 File name: Save Save as type: Block Diagram/Schematic File ( bdf Cancel Add file to current project tD
    
15. Now comple the project by clicking on the play button above, wait for successful compilation.
16. Now we go for the simulation.
17. Create a new Simulation Input file. Here the “Vector WaveformFile’ format is used to define simulation inputs. For this , File menu -> select ‘New’ -> select ‘Vector Waveform File’ in the ‘Other Files’ tab on the ‘New File’ Dialog box-> press Ok ->go to the ‘View’ menu ->select ‘Utility Windows’ ->select ‘Node Finder’
18. We will use ‘Node Finder’ to select input
    nodes of our newly designed circuit. Drag it to the vector waveform file designated area.
19. Select waveform editing tool And drag to the input we need to get the output waveform. Create a waveform for each input
20. Now again save the simulation. Press start simulation , the play button on above toolbar. After successful simulation we get the correct output.
    New Other Files Device Design Files Software Files AHDL Include File Block Symbol File Chain Description File Hexadecimal (Intel-Format) File Memory Initialization File SignalTapIl File Tcl Script File Text File Vector Waveform File OK Cancel *New File' Dialog box for creating a new simulation file based upon Vector Waveform File' format uartus II-c:/documents and settings/waseem/my documents/waseem/teaching/ece46 File Edit View Project Assignments Processing Tools Window Help Project Navigator Utility Windows Alt+0 Node Finder Ic Console Messages Alt+1 Full Screen Ctrl+Alt+Space Alt+2 ty Fit in Window Compilat Zoom In Ctri+W Alt+3 Ctri+Space Alt+4 Status Den Zoom Qut Ctrl+Shift+Space Change Manager Alt+5 Zoom... Compare to Waveforms in File... End File Comparison Next Iransition Right Arrow Left Arrow Previous Transition Show Original Waveforms Only Show Compared File Waveforms Only Show Both Sets of Waveforms Ctrl+ Ctrl+2 Ctri+3 Show Comments Snap to Transition 8 Snap to Grid Selecting the Node Finder' tool
    
    s/waseem/my documents/waseem/teaching/ece465/spring05/demo s05/Demo 505-Demo S05-[Wa Processing Tools Window Help A? Demo_S05 x 15.275 ns 100 ps Master Time Bar Pointer Named 10.0 0 ps A Filter Pins: all Value at 15.28 ns Name Customize. Look inDemo S05 Include subentities List Stop YaNodes Found Name A B DO 4D1 D2 D3 Ve The input and output nodes enumerated by 'Node Finder' tool waseem/my documents/waseem/teaching/ece465/spring05/demos05/Demo S05-Demo 505-[Waveform1.vw ocessing Tools Window Help ? Demo s05 RPointer: Master Time Bar Interval 15.275 ns 100 ps Named 100 ns 0 ps A Filter Pins: all Value at 15.28 ns Name Customize. B0 A Look in: Demo S05 B0 Include subentities List Stop C Nodes Found Name DO D1 D2 D3 L Dragging input nodes onto the simulation input file
    
    Value at 15.28 ns Name B 0 Waveform Editing Tool B O The 'Waveform Editing Tool highlighted 240 160,0 ns 800 ns 0 ps Value at 15.28 ns Name 275 ns A B 1 B 0 B Using 'Waveform Editing Tool' to create waveforms for input nodes A and B Poiter Stat 15.275 ns 507.75 ns Master Time Bar Interval 492 48 n End 160,0 ns 960,0 800ns 240,0 ns 320,0 ns 400,0 ns 480,0 ns 560,0 ns 640,0 ns 720,0 ns 800,0 ns 880,0ns ps 275 ns A Value at 15 28 ns Name A B 1 B0 The simulation waveforms for inputs A and B ATAI 2A
    
    Save As X Demo S05 Save in db File name: Demo S05 Save Save as type: Vector Waveform File (vwf) Cancel Add file to current project Saving the Vector Waveform File' format based simulation input file for decoder circuit. 266.98 ns Start Simulation 320 0 ns "Start Simulation' button highlighted 240 0 ns 40n n ns Simulation Waveforms Pointer Master Time Bar 15.275 ns Interval 400,0 ns 0 ps 275 ns 800 ns 160,0 ns 320,0 ns 240,0 ns Value at 15.28 ns Name B 1 A B B0 DO B0 D1 B0 D2 B 1 D3 B0 Quartus II Simulation was successful (0 errors, 0 warnings) OK Simulation Results