computer architecture and organization




computer architecture and organization Figure Q20 shows a space time diagram to execute n instructions by...
(Pipelining 20%) The 5 stages of a processor have the following latencies: Fetch Decode Execute Memory Write-back 250 350ps 300ps 500ps 80ps a. If the processor is non-pipelined: what is the clock cycle time for the processor? What is the latency of an R-type instruction in the processor? b. If the processor is pipelined: What is the clock cycle time for the processor? What is the latency of an R-type instruction in the processor? C. If you could split one...
The latencies of individual stages in five-stage MIPS (Microprocessor without Interlocked Pipeline Stages) Architecture are given below. Instruction Instruction Fetch Register Read Arithmetic Logic Unit (ALU) Memory Access Register Write Latency 200ps 100ps 200ps 300ps 100ps a. (10 pts) What is the clock cycle time in a pipelined and non-pipelined processor? Pipelined version : ______________ Non-pipelined version : ______________ b. The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the followings: Register write is done...
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2. A certain program has the following instruction classes, CPIs, and mixtures: Instruction Type CPI ratio 1.5 .40 2.1 .35 3 a. What is the average CPI for this processor? b. You have the following options: • Option 1: Reduce the CPI of instruction type B to 1.8 • Option 2: Reduce the CPI of instruction type C to 2.5 Which option would you choose and why? 3. Consider...
26. The is a group of bits that tells the computer to perform a specific operation A). program counter B). Opcode C). register D). microoperation 27. A condition called occurs in unsigned binary representation of a number when the result of an arithmetic operation is outside the range of allowable precision for the given number of bits. A). underflow B). 2's complement C). overflow D) bitwise complement 28. An iteration of the fetch-decode-execute cycle includes which of the following events?...
Computer Architecture 14. Fill in the blanks below with the most appropriate term or concept discussed in this chapter: A. ---------------The time required for the first result in a series of computations to emerge from a pipeline. B. ---------------This is used to separate one stage of a pipeline from the next. C. ---------------Over time, this tells the mean number of operations completed by a pipeline per clock cycle. D. ---------------The clock cycles that are wasted by an instruction-pipelined processor due...
Computer
architecture
Question 39 25 How does the superscalar CPU commit the instructions? The instructions, in program order, are: A, B, C, D, E, F. The instructions execute in the order shown below. After each instruction is executed, mention which instructions) are committed at that point. E n ✓ Choose Commit E, F None committed Commit D, E, F Commit B,C Commit C, E Commit A Commit B, C, E A 4 [Choose) B [Choose] F [Choose) D
Consider the implemented of two different processors P1, and P2 with the same instruction set architecture (ISA). P1 has a 2 GHZ clock rate and P2 has a 2.5 GHz clock rate. a. what is the clock cycle for each processor? b. If the CPI for a program A is 2, which processor has the highest performance? c. if the processors P1 execute the program in 2 seconds, find the number of instructions. d. We are trying to reduce the...
Computer Architecture
The format of this document is as follows: First, I give
a practice problem for which the solution is also provided. In bold
italic font, I slightly modify the problem for your
homework.
3) The 4-Stage Pipeline below suffers from the memory access
resource conflict as shown below (instruction i and i+2 want to
access memory at the same time and i+2 needs to be denied, so it
waits for the next cycle; in the next cycle it...
Figure 1: each block gives the number of different types of instructionsConsider a program with the execution flow shown in Figure 1. There are in total 3 types of instructions used in this program: Type 1 (in-processor calculation): execution rate as 1 per clock cycle; Type 2 (memory access): each instruction takes 2 clock cycles for execution; Type 3 (loop control): each instruction takes 2 clock cycles for jump into the loop block or 3 clock cycles for jump to the block after...
please i need a good answer and a perfect answer.. i need unique
answer use your own words.
please i need a good answer and a perfect answer.. i need unique
answer use your own words.
please i need a good answer and a perfect answer.. i need unique
answer use your own words.
don't use handwriting
Q3:
a) Specify the two factors used to determine the capacity of
memory. Find out the memory capacity, if the number of bits...