Question

1 Pipeline: A (fictional) CPU has the following internal units and timings (WR and RR are write/read registers, ALU does all logic and integer operations and there is a separate floating point unit. RR 40ps ALU-INT 180ps ID 180ps MEM 200ps WR 60ps WR 60ps FP 280ps There are 5 basic instruction types: 1. LOAD : ID+RR+ALU+MEM+WR: 660ps 2. STORE: ID+RR+ALU+MEM: 600ps 3. LOGIC/INTEGER: ID+RR+ALU+RW: 460ps 4. FLOATING POINT: ID+RR+FPU+RW: 560ps 5. BRANCH: ID+RR+ALU: 400ps 1 cycle is 660ps for the unpipelined machine, on the assumption that all instruc- tions take 1 cycle (ignore memory delays). Design a pipeline for this machine. 1. How many stages and which functional units in each stage 2. What is the new clock rate and what is the speedup.

Answer 1

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Answer:

stages LOAD Pipeline diogram :- a tu in each stages c ca cs C4 C5 C6 TID IRR IALUI MEM|WR I C7 STORE DO RR 20 ALU MEM] RR | ALU , Rol LOGIC RR PU FLOATING POINT Arros on bot Fru | R੩) to lar | Alvy RR BRANCH : These are s stages can be used ca the Pipeline.

Speedelp :- Speedup - Pipeline depth clock cycle unpipeline I + Pipeline start CPP clock cycle Pipelined = * 5 to 660 CLK I clock cycle pipelined :- KA(n-1) k is . a Num of stage. = 600 660 TO * second 600 = 5 *lil Speedup = 5.5