Question

5. The DFG shown in Fig. 4.19 describes a 4th-order IIR digital filter implemented as cascade of 2 2nd-order sections. Assume each multiply requires 2 u.t. and add requires 1 u.t. (a) What is the critical path of this DFG? What is the iteration bound of this DFG? (b) Manually retime and pipeline the DFG to minimize the clock pe riod. What is the minimum achievable clock period obtained with pipelining and retiming?

Answer 1

al Critical path is delay free path which is maximum A2 → A4 → A6 A8 which is Consider the path My →A1 delay free and maximum also Multiplier — 24t Adder - lut 2+1+1+1 12 7ut. Loop boundi = tittet ittn ti, t2, - th are computation time of each node 1,2,3-n respectively. Ki KitKat-kn total no. of delays in the loop | (A2 M2 A1 A2) d = 241 41 41 = 4 Imultiplier, 200 I- A2M2 A 12 contains (A2 My A1 A2) da= 2+111 4/2 = 2 (Loop Az My Al Al contains 2-delays, Imultiplier, 2adders) . iberation bound = Too max (41122) = max (412) To = 4ll

achievable clock period itoration bound tells about minimum fut. So we can decrease clock period upto qut from After retiming of: 5 . - to consider the above DEG cohich is ret imed (M2A A2) it has critical path of uut which is minimum achievable time period we can't go beyond uut.