Question

Problem 8 (Lab, 20 points) (1) Write a VHDL module implementing a synchronous 16-bit counter. A "reset signal resets the counter to 0. An "en" signal enables the counter modification. An "up signal indicates whether the counter must be incremented (1)/decremented (0). (2) The output of the module is the value of the signal, represented as 16 bits wide. Using output timing diagram to verify your coding results.

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter_updown is
port (
clk : in std_logic; -- clock input
reset : in std_logic; -- reset
en : in std_logic; -- enable
up : in std_logic; -- up = 1 when counter counts in up direction otherwise dowm direction
Q : out std_logic_vector(15 downto 0) -- output data
);
end counter_updown;

architecture behavioral of counter_updown is
signal temp : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then -- When reset = '1'
temp <= (others => '0');
elsif (en = '1') then -- when CE = '1'
if (up = '1') then
temp <= temp + '1'; -- counting in up direction
else
temp <= temp - '1'; -- counting in down direction
end if;
else
temp <= temp;
end if;
end if;
end process;
  
Q <= temp;

end behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity counter_updown_tb is
end counter_updown_tb;

architecture behavior of counter_updown_tb is
-- component declaration for the unit under test (uut)
component counter_updown
port(
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
up : in std_logic;
q : out std_logic_vector(15 downto 0)
);
end component;
  

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal en : std_logic := '0';
signal up : std_logic := '0';

    --Outputs
signal Q : std_logic_vector(15 downto 0);

-- Clock period definitions
constant clk_period : time := 10 ns;

begin

   -- Instantiate the Unit Under Test (UUT)
uut: counter_updown port map (
clk => clk,
reset => reset,
en => en,
up => up,
Q => Q
);

-- Clock process definitions
clk_process :process
begin
       clk <= '0';
       wait for clk_period/2;
       clk <= '1';
       wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin      
reset <= '1'; en <= '0';
wait for clk_period*10;
reset <= '0';
en <= '1'; up <= '1';
wait for 100 ns;
       en <= '0'; up <= '1';
wait for 50 ns;
       en <= '1'; up <= '1';
wait for 300 ns;
       en <= '0'; up <= '1';
wait for 100 ns;
       en <= '1'; up <= '0';
       wait for 200 ns;
       en <= '0'; up <= '0';
wait for 100 ns;
       en <= '1'; up <= '1';
wait for 100 ns;
       wait;
end process;

end;

Waveform

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