Question

1. Write synthesizable VHDL code for an 16-to-1 Mux. The inputs are wo, wl, w2, w3, w4. w5, 16, w7, w8, w9, w10, wil. The last four inputs are not connected to an input signal. How many select bits requires the circuit? Draw the schematic of your Mux, showing the inputs and outputs of the circuit

Answer 1

1907 MAYTISVITTOO TO TOTT ZSTAVOTOTY Solution 1p 8 = Wo, ws, ..... W11. (12 ilp's). for 16 to 1 mux we need A Select lines. > 24. 16 Here n indicates nof. of 4 Select Lines n=1 Select lines U w 101 To Schematic of 16 to 1 Mux Not connected to ile. so se si 50 4 Select Lines

Library IEEE; We TEEE.STD-LOGIC -1164.ALL; Le TEEE. STD-LOGIC - Undygned. Au --because we z for last HW Entity mustitto1 if Poat (wow),2,3,4,5,6,7,8,109,110,11; in STD-LOGIC) -- 11 Pnput declaration S:in &td-logic Vector (3 dowonto 0); -- Select line 4bits F: Out Std-logic); end muxlbtos; architecture behavioral of muxlitoi 18 begin process cs) begin case s is when "DOOD" >F<> Wo" -- Dpf Law (based on select the when "Oooh Flow when "D01D" >FL-W2 when "00" > FLOW3; when "100" F W4 when "0101 -> FLOWS: when "010" =>FLW6: when "01" >FL:w , when "1000" > Flaws when "100" >> Flow: when "1010" - FLEWO: when "1011" Flawll; when othes 8 -> FLO'Z'; -- fez Cheghimpe dana) --for alp's 2012, wis, win, 15) end case; --FL= '0' we can also end Prolet end behavioral; - use this so last 4 /20.

two different waveform for F=Z and F=0 which is a default case for last 4 inputs as we were not connecting the last for inputs to mux

3 File Edit View ΜΕ Simulation Window Layout Help Κ Α Σ και 8 ) (M) 6 Ο Ξ Ξ Ξ Ξ ? Ρ Β Ε Ε 14 15 16 46.870 πς Name 150 Πς ΙΒΟ Πς 40 ns 20 ης Vali 12 τ. . 10 το.. 59.........70 το...βο το 0000 πΧ οοΙ τοαιX 0001 το0 X 0001 τοΙΧ 001 Χ τιοι λότοι τττοΧοττο ΙουλOIO0 10000000 X2: 46.870 ης

ΑΙ Α) Ο ΗΞΕΡ + ΣΕ ΕΕ και τη 14.200 ns Name Valdons 10 ns |20 ns 130 ns 140 ns 40 25. 50 III, 50 .1 .60 της... .. Ι O I 0000 X 0001 Υ 0010IX 0011 Χ 1000Χ1001 0110 X 01111000 Χ 1001 1010 Χ 1011 1100 Χ 101100 Xος Θ010 X1: 14.200 πς 1 ΠΕ 1