Homework Answers
Here are the answers:
a) ADD r0, r1, r1, LSL #2 is same as
r0 = r1 + r1 * (2 ^ 2)
r0 = r1 + r1 * 4
r0 = r1 * 5
r0 = EA0D11FD * 5 = 4924159F1
b) ADD r0, r1, r1, ASR #4 is same as
r0 = r1 + (Shift contents of r1 RIGHT by 4 bits)
r0 = r1 + (Shift EA0D11FD RIGHT by 4 bits)
r0 = EA0D11FD + EA0D11F = F8ADE31C
c) ADD r0, r1, r1, ROR #7 is same as
r0 = r1 + (Right Rotate r1 by 7 bits)
r0 = EA0D11FD + (Right Rotate EA0D11FD by 7 bits)
r0 = EA0D11FD + FBD41A23 = 1E5E12C20
ASSEMBLY CODE NEED ASAP WILL RATE RIGHT AWAY all Verizon 6:48 PM What will r2 contain...
ASSEMBLY CODE NEED ASAP WILL RATE RIGHT AWAY
all Verizon 6:48 PM What will r2 contain after the execution of the following instructions assuming that the instructions are executed independently? given that initially r2=0XFFFFFFFF r1=0xFF00FF00 and r0= 0xF7 1) MVN r2, 0x7E000000 2) EOR r2,rO,r1; 3) ROR r2,ro,#2; 4)MLA r2,r2,r2,rO 5) RRX, r2,r& initial carry flag =1 6) MOV r2,(14<<3) 7)ASR r2,r1,#1 8)LSL r2,r1,#3 9) LAR r2,r1,#3
Consider the following loop. loop: Iw r, 0(r1) 9. and rl, r1, r2 lw ri, o(ri)...
Consider the following loop. loop: Iw r, 0(r1) 9. and rl, r1, r2 lw ri, o(ri) lw r1, O(r1) beq rl, rO, loop that perfect branch prediction is used (no stalls due to control hazards), that there are no delay Assume slots, and that the pipeline has full forwarding support. executed before the loop exits. A - Show a pipeline execution diagram for the third iteration of this loop, from the cycle in which we fetch the first instruction of...
Ox00000000. Initially N-Z=C=V=0. Find the new values ofr3, N, Z, C, and V running each following...
Ox00000000. Initially N-Z=C=V=0. Find the new values ofr3, N, Z, C, and V running each following instructions 5. Suppose r0 0XFFFFFFFF, rl = 0x00000001 and r2 independently (i.e. same starting values for each case). Not graded: check results with TIVA. ADDS r3, r0, r2 а. b. SUBS r3, r1, r0 ; note: not the LSLS instruction r3, r0, #1 LSL с.
A C program has been compiled into the Atmel AVR assembly language. The following instruction, which...
A C program has been compiled into the Atmel AVR assembly
language. The following instruction, which is located at address
0x002A, is executed:
i.) What is the binary value contained in the instruction
register (IR) when the instruction is executed?
ii.) What is the hexadecimal value of the program counter (PC)
when the instruction is executed?
iii.) If register r1 = 0x40 and register r2 = 0x02 prior to
executing the instruction, what are the contents of r1 and r2...
Assume SP = 0x20001010 before the following instructions are executed: MOV R0, #0 MOV R1, #1 MOV ...
Assume SP = 0x20001010 before the following instructions are executed: MOV R0, #0 MOV R1, #1 MOV R2, #2 PUSH {R0, R1, R2} After these instructions execute: What is the value of the SP? _________________ What is the value of the following memory locations (place X in the blank if it cannot be calculated): Address 32-bit Data 0x2000101C ____________ 0x20001018 ____________ 0x20001014 ____________ 0x20001010 ____________ 0x2000100C ____________ 0x20001008 ____________ 0x20001004 ____________ 0x20001000 ____________
Suppose we have a hypothetical processor, of which each register has only five bits. r0 =...
Suppose we have a hypothetical processor, of which each register has only five bits. r0 = 0b11101 and r1 = 0b10110. What are the N,Z,C, and V flags of the following instructions? Assume initially N = 0, Z = 0, C = 1, V = 0, and these instructions are executed independently (1) ADDS r3, r0, r1 (2) SUBS r3, r0, r1 (3) EOR r3, r0, r1 (4) ANDS r3, r1, r1, LSL #3
3) (5) What value will the carry flag contain after these instructions: a) MOV R1,#3 MOVS...
3) (5) What value will the carry flag contain after these instructions: a) MOV R1,#3 MOVS R2, R1, LSR #1 b) MOV R1,#2 MOVS R2, R1, LSR #1 4) (5) Will this instruction update the flags in the CPSR? ADD R1, R0, #1 Alo it Why or why not?
Suppose r0 = 0 times 20008000, and the memory layout is as follows: (a) What is...
Suppose r0 = 0 times 20008000, and the memory layout is as follows: (a) What is the value of r1 after running LDR r1, [r0] if the system is little endian? What is the value if the system uses the big-endian? b) Suppose the system is set as little endian. What are the values of r1 and r0 if the following instructions are executed separately? LDR r1, [r0, #4] LDR r1, [r0], #4 LDR r1, [r0, #4]!
Problem: On an ARM processor using big endian format, given the following memory map and [R1]...
Problem: On an ARM processor using big endian format, given the following memory map and [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C, predict [R1] and [R2] and draw the updated memory map after an ARM data transfer instruction is executed in EACH case. (hint: (1) in this map, each memory location is a word long and occupies 4 bytes; also you only need to draw the section of the memory including the changed word and...
Problem: On an ARM processor using big endian format, given the following memory map and [R1]...
Problem: On an ARM processor using big endian format, given the following memory map and [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C, predict [R1] and [R2] and draw the updated memory map after an ARM data transfer instruction is executed in EACH case. (hint: (1) in this map, each memory location is a word long and occupies 4 bytes; also you only need to draw the section of the memory including the changed word and...
ASSEMBLY CODE NEED ASAP WILL RATE RIGHT AWAY
all Verizon 6:48 PM What will r2 contain after the execution of the following instructions assuming that the instructions are executed independently? given that initially r2=0XFFFFFFFF r1=0xFF00FF00 and r0= 0xF7 1) MVN r2, 0x7E000000 2) EOR r2,rO,r1; 3) ROR r2,ro,#2; 4)MLA r2,r2,r2,rO 5) RRX, r2,r& initial carry flag =1 6) MOV r2,(14<<3) 7)ASR r2,r1,#1 8)LSL r2,r1,#3 9) LAR r2,r1,#3
Consider the following loop. loop: Iw r, 0(r1) 9. and rl, r1, r2 lw ri, o(ri) lw r1, O(r1) beq rl, rO, loop that perfect branch prediction is used (no stalls due to control hazards), that there are no delay Assume slots, and that the pipeline has full forwarding support. executed before the loop exits. A - Show a pipeline execution diagram for the third iteration of this loop, from the cycle in which we fetch the first instruction of...
Ox00000000. Initially N-Z=C=V=0. Find the new values ofr3, N, Z, C, and V running each following instructions 5. Suppose r0 0XFFFFFFFF, rl = 0x00000001 and r2 independently (i.e. same starting values for each case). Not graded: check results with TIVA. ADDS r3, r0, r2 а. b. SUBS r3, r1, r0 ; note: not the LSLS instruction r3, r0, #1 LSL с.
A C program has been compiled into the Atmel AVR assembly
language. The following instruction, which is located at address
0x002A, is executed:
i.) What is the binary value contained in the instruction
register (IR) when the instruction is executed?
ii.) What is the hexadecimal value of the program counter (PC)
when the instruction is executed?
iii.) If register r1 = 0x40 and register r2 = 0x02 prior to
executing the instruction, what are the contents of r1 and r2...
3) (5) What value will the carry flag contain after these instructions: a) MOV R1,#3 MOVS R2, R1, LSR #1 b) MOV R1,#2 MOVS R2, R1, LSR #1 4) (5) Will this instruction update the flags in the CPSR? ADD R1, R0, #1 Alo it Why or why not?
Suppose r0 = 0 times 20008000, and the memory layout is as follows: (a) What is the value of r1 after running LDR r1, [r0] if the system is little endian? What is the value if the system uses the big-endian? b) Suppose the system is set as little endian. What are the values of r1 and r0 if the following instructions are executed separately? LDR r1, [r0, #4] LDR r1, [r0], #4 LDR r1, [r0, #4]!
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