Question

EFE3096S L23 to 125 Arthmetic and Logical Operations.pcf Adobe Acrohat Reader DC File Edit View Window Help Home Tools EEE3096S-123 to L. EEE3096S-L26 to L EEE3096S-L28 Wh... EEE3096S-129 Mo EEE3096S-L30 Mo... sign In 山Share Arithmetic and Logical Operations Arithmetic Logic Unit: Question 3 Design an arithmetic circuit for the ALU above, which has a 3-bit instruction set. The opcodes in the instruction set are provided in the table below. Only design the system for the 1-bit case. You have the following components available to you: 1-bit full adders, multi-bit wide multiplexors, AND, OR, NOT, NOR, NAND and XOR gates, decoders etc. Opcode Operation A+ B A- B A+ B B-A 0 1 A+1 Embedded Systems lIl EEE3096S R. Verrinder Y. Abdul Gaffar 34.

Answer 1

In this design, we are given with the opcodes, that are 8 in number. On fetching any one of the opcode at a time, one of the 8 operations is performed. I have drawn main circuit in figure 1 and the intermediate inputs used are represented in subsequent figures.

fig2- General block diagram of 1Bit full Adder {abbreviated as 1BA}. a,b,C_n-1 are inputs and S_n & C_n are sum and carry outputs respectively.

fig3: Addition of A and B using 1 full adder.

fig4: A-B=A+(-B)=A+(2's complement of B)=A+(Bbar+1).................Bbar is complement of B.

fig5- Abar+B, using full adder and not gate

fig6_1: B-A=B+(Abar+1)

fig6_2: A-1=A+(1bar+1)=A+(0+1)

fig7: A+1

fig8: Abar+1

The 'sum' outputs, viz S0 to S7 {except S6} are taken from fig 3-8 and used in figure 1.

M5 & M7 are projected directly to AND gate (fig1) due to space constraint.

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