Question

Problem I (Codes, 6 Pts) Design a circuit that takes as input an ASCII-coded symbol (7 bits) and generates it parity bit. Consider for this problem the even parity. Problem II (Codes, 5 Pts) Consider a heat monitoring system containing an internal temperature sensor that produces different levels of voltage depending on the ambient temperature. The following table summarizes the possible voltage outputs: Temperature Decreasing 2.7V 3.0 v 3.3 V 3.6V 3.9 V 4.2 v 4.5 V Temperature increasing We wish to represent these voltages in computer for further processing. The conversion is done using an analog-digital-converter. Provide an optimal binary coding. That is a coding that reflects the behavior of the analog device. Small changes on the analog side cause small movements on the binary side.

Answer 1

Problem 1

We have been asked to make a circuit that takes in seven bits as input and generates one bit as output. It is obvious that we need to make use of combinational gates to achieve this.

When we think of combinational gates that have something to do with parity, we think of the XOR gate. The reasoning behind this will be explained shortly.

A quick revision - the exclusive or (or simply XOR) gate takes two bits as inputs and returns a one as output if and only if one of the inputs was a one. Two interesting points to note about the XOR operation is that it is commutative and associative. In other words,

A B = B ФА

and

АФ (ВФС) = (A+B) ФС,

where A, B, and C are three binary numbers. This result is easy to prove (just consider all 8 cases) and it's crucial to the problem at hand. It shows us that when we have only XOR operations, the order that the inputs are taken in doesn't matter. This is something one might link to the generation of the parity bit. (For example, the binary words 1001101 and 1111000 both have the same parity because the bits of one words are just the bits of the other word, taken in a different order.)

Consider the process of XORing three bits in succession. This is shown in the following statements:

ОФОФ0 = 0

10000=1

1e100=0

$1\oplus 1 \oplus 1= 1$

Note that because the XOR operation is commutative and associative, the four statements above account for every possible case of three bits being taken as inputs to the process.

You may notice that whenever the number of ones in the input to the process was odd, the output of the process was a one. The output was a zero if and only if the number of ones in the input was even. This is something that rings true when XORing any number of bits. As such, the XOR gate functions as an odd-one detector.

When generating even parity, we add a one if the number of ones in the symbol was odd, and we add a zero otherwise. It becomes obvious now why the XOR gate is important. If the bits in the 7-bit symbol are represented by b0, b1, b2, ... b7, then the parity bit will be given by:

$p=b_0\oplus b_1\oplus b_2\oplus b_3\oplus b_4\oplus b_5\oplus b_6$

If we needed to generate odd parity, we'd have to take the above result and flip it. This could be accomplished through either a NOT gate or by XORing the above result with 1.

Problem 2

There are a total of 7 possible values, so we estimate that to represent them, we'd need a number of bits equal to $\small \lceil log_2(7)\rceil = 3.$ Let the word generated by the ADC be a0a1a2, with a0 being the most significant bit, and a2 being the least significant bit.

We can keep the 3.6 V value in the middle of our scale, and say that values greater than this will have a0 = 1; values less than or equal to 3.6 V will have a0 = 0. Thus, our coding scheme would look like this:

Voltage value	Word
2.7 V	000
3.0 V	001
3.3 V	010
3.6 V	011
3.9 V	100
4.2 V	101
4.5 V	110

Notice that if the voltage values of two inputs differ by 0.3 V, the corresponding words differ by a value of "one". (In other words, if a binary value of one is added to the smaller word, we end up with the next word). This is important because it means that small changes in the voltage correspond to small changes in the output word.