Question

Q3. Synchronous Counter Figure 8.3(a) shows a modulo-8 synchronous up-counter (Modulo-8 because this counter can count only from 0 to 7 with its 3 bits qo, q1 and 92.). Treat each gray cell in the figure as a component and write generic VHDL codes to create a modulo-2N counter, where N is the number of flip-flops required. Use nominal mapping for this problem while instantiating components. When the asynchronous reset signal rst is high, the counter is set to 0 (active-high reset). Show that your circuit works as a counter with N = 3 via simulation for 10 clock cycles as shown in figure 8.3(b). clk rst Figure 8.3(a) Synchronous counter for Q3.

Answer 1

I have tried to answer the question using Verilog code. Hope it helps.

Feel free to ask if you have any querry..!!

Code for one grey cell -

module block( clk,rst ,x,y,q,r);
input clk,rst,x,y;
output reg q;
output r;
wire d;
always @ (posedge clk or posedge rst)
begin
if (rst)
q =0;
else
begin
q = d;
end
end
assign r = x && y;
assign d = (q && (~r)) || ((~q) && r);
endmodule

Code for combined module having three grey cells instantiated and connected as per the figure -

Note - Here I have used one more output naming "out" which shows the count together using three

module top( clk,rst,q0,q1,q2,out);
input clk, rst;
output q0,q1,q2;
output [2:0]out;
wire r1,r2,r3;
block b1( clk,rst ,1'b1,1'b1,q0,r1);
block b2( clk,rst ,r1,q0,q1,r2);
block b3( clk,rst ,r2,q1,q2,r3);

assign out = {q2,q1,q0};
endmodule

Test bench to check the above codes-

module top_tb;
reg clk,rst;
wire q0,q1,q2;
wire [2:0] out;
top t1( clk,rst,q0,q1,q2,out);
always
begin
clk =1; #5;
clk =0; #5;
end
initial
begin
rst =1;
#1;
rst =0;
end
endmodule

Here are the simulation results-

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