Question

It has four output patterns: 000, 001, 0111 Tho Te two control signals e counter counts when it is 1 and the counter pauses when it is 0 e counter "increases" (circulating through 000, 0011, 01, 111 and .....pping around) when it is 1 and go is 1. The counter "decreases" (circulating in a reversed pattern, ie., 1 1 11, 01 11, 0011, 0001, and wrapping around) when it is 0 and g0 is l The circuit can be constructed by an FSM with four states (two D FFs). The inputs of the circuit are clk: clock signal reset: the reset signal to force the FSM to its initial state (0001) go: control signal defined above · . inc: control signal defined above The outputs of the circuit are q1,q0: outputs of D FFs, which show the current state of the FSM m3, m2, m1, m0: outputs of the counter 4 Procedure 4.1 Counter FSM (a) Derive the state diagram (with four states) (b) Derive the state table (c) Perform a state assignment with a minimal number of FFs (d) Use D FFs to realize the FSM and derive the next-state truth tables and output truth table. (e) Derive next-state equations and output equation. (f) Create a project in Altera Quartus II software and enter the schematic. D FF symbol can be found by selecting libraries -primitives-storage-df (g) Create a testing waveform with a clock period of 200 ns and perform simulation. The testing waveform should demonstrate the operation of FSM and the effect of control signals (h) Create a symbol in Quartus II to be used in the next part

Answer 1