Question

1. Consider the following Verilog code. wire [3:0] a, b, c, d, e assign a 4'b1010; assign ba assign ca>> assign d a>>1: assign e a+b Which of the following choices represents the values after executing this Verilog code? b 4,b1010, c- 4'b0 101, d . 4'b1 101, e " 4,b0000 (b) ar itr four 7-sepment displays:

Answer 1

Given verilog code is wire [3: 0] a, b, c, d, e: assign a = 4�b1010: assign b = ~a: assign c = a > > 1: assign d = a > > 1: assign e = a + b: Here b = ~a =~1010 b = (0101)_2 c = a > > 1 This means shift a right by 1 bit, fill with zero = 1010 > > 1 t = (0101)_2 d = a > > > 1 This means shift right 1 bit, fill with value of signed bit if expression is signed here signed represented by a > > 1. The session is based on signed bit. Therefore d = (1101)_2 e = a + b = 1010 0101 1111 e = (1111)_2 therefore option (a) is correct