Question

Q49.

J Q49 Assume this counter is initially reset at clock pulse "0". Draw the output waveforms AA, B, and C for one complete cycle of operation in the waveform chart below the schematic. Use positive logic More clock pulses have been provided than may be required. You need not continue the waveform beyond the clock pulse that resets the counter again.

the circuit and waveforms is the only infos I have. I will rewrite the question:

Assume this counter is initially reset at clock pulse "0". draw the output waveforms AA, B, and C for one complete

cycle of operation in the waveform chart below the schematic. Use positive logic. More clock pulses have been provided than may be required. You need NOT CONTINUE the waveform beyond the clock that resets the counter again.

looks like some infos are missing just try your best thanks.

Answer 1

J K flip flop truth table Initially all flip flops in reset state A = 0: B = 0: C = 0 therefore the counter lock's between the 111 and 110 states

If you have any doubts please comment

Thank you