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We’re executing the following instruction sequences on a 5-stage MIPS pipeline. Add R8, R9, R10 Lw...

We’re executing the following instruction sequences on a 5-stage MIPS pipeline. Add R8, R9, R10 Lw R14, 0x0020(R12) Or R16, R9, R10 Sw R12, 0x0020(R10) Addi R20, R21, 5 (1) At cycle 5, what action (add, sub, and, or) is ALU performing? (2) At cycle 5, what is the action (read, write, no action) of DM? (3) At cycle 5, which registers are being read out? (4) What is the speedup comparing with the unpipelined execution of the same instruction sequence?

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pipe line diagram Cloud instruction 2 34 5 67 10 Add R8 Rg Rio IF ID EX mem| WB LW R40 20(812) IF ID EX(mem WB Or RIG Rg Rio

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