Question

Prove that the cnfsat <p neqcnf. This is a reduction by restriction.

NP-Completeness

Answer 1

Proof:
Clearly, 3-CNF-SAT is in NP; we just use a satisfying assignment as the linear-time verifiable certificate. So we just need to show CIRCUIT-SAT <_p 3-CNF-SAT.

From a circuit C made up of gates AND, OR, and NOT, and input variables in a set { 1 .. n}, we will construct a 3-CNF formula F that is satisfiable if and only if F is satisfiable. The construction goes as follows:

1. For each variable in C, there is a corresponding variable in F.
2. For each gate c in C, there is a corresponding variable f in F.
3. For each NOT gate c modifying a gate or variable d in C, insert logic into F stating "c is equivalent to NOT d." This can be accomplished in CNF with two clauses: (d OR c and (NOT d OR NOT c). If you don't quite buy this, let's see how it's true with a truth table:

   c  d  (d OR c)  (NOT d OR NOT c)  ((d OR c) AND (d OR NOT c))  d == NOT c
   -  -  --------  ----------------  ---------------------------  ----------
   F  F     F             T                     F                     F
   F  T     T             T                     T                     T
   T  F     T             T                     T                     T
   T  T     T             F                     F                     F
   

4. For each AND gate c modifying two gates or variables d and e in C, insert logic into F stating "c is equivalent to d AND e." We can do in CNF with the following clauses:

   NOT c OR d
   NOT c OR e
   c OR NOT d OR NOT e

   This can be shown using another (eight line) truth table.
5. For each OR gate c modifying gates or variables d and e, insert logic into F stating "c is equivalent to d OR e." We can do this in CNF with the following clauses:

   c OR NOT d
   c OR NOT e
   NOT c OR d OR e

   This can also be shown with a truth table.
6. Note that we can omit either AND or OR, simulating one with a combination of NOT and the other, making the circuit a little bigger. We can also simulate any other logic gate (NAND, NOR, XOR, etc.) as combinations of AND, OR, and NOT in linear space.
7. For the output gate c of the circuit, insert logic into F stating "c is equivalent to True." The singleton clause (c) states this.

We now have a formula F that defines the operation of the circuit, describing from the variables through the gates to the output the precise value on the output of each gate. The formula can only evaluate to True (i.e. be satisfied) if there is some assignment to the inputs of the circuit that make the output True. This transformation is carried out in linear time and space: only up to three clauses are needed for each gate, so for a gate with n gates, the resulting formula has (n) clauses. Thus, 3-CNF-SAT is NP-hard and, being in NP, is NP-complete. []

We don't seem to have accomplished much with this proof; we've replaced one kind of pointy-headed Boolean logic problem with another. However, note that 3-CNF-SAT is a much restricted version of CIRCUIT-SAT. We can use 3-CNF-SAT to prove other problems are NP-complete in instances when tackling all of CIRCUIT-SAT is infeasible or impossible. That is, 3-CNF-SAT is easier to work with when proving things NP-complete.

(Note: It turns out k-CNF-SAT, where clauses have at most k literals, is NP-complete for k > 2. For k = 2, (i.e. 2-CNF-SAT), there is a polynomial time algorithm: a clause (a OR b) is the same as (NOT a IMPLIES b); make a directed graph with vertices the literals and edges the implications derived from the clauses; if any strongly connected component (computable in linear time, similar to the connected components in undirected graphs we saw with Union/Find) of the graph contains a literal and its complement, that is a contradiction, so the formula is not satisfiable. Otherwise, it is. Unfortunately, this algorithm doesn't extend to k-CNF-SAT for k > 2, so we don't get to prove P=NP this way.)

Now let's look at a problem we saw last time: