HomeworkLib
Question

Consider the following sequential circuit, which has no external inputs. REG3 is a 3-bit register. REG3 DO 00 00 DI 01 Q1 XOR

Present State Next State Q2 Q1 QO D2 D1 DO 0 0 0 0 0 0 0 1 1 0 1 10 0 0 1 0

Also explain in words what this means. Assuming that Q2 Q1 and Q0 are LEDs from left to right respectively, and D2, D1, and D0 are switches from left to right respectively. Just explain a few states for my understanding.

engineering   Electrical-Engineering   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

When the present state is Q2 = 0, Q1 = 0, Q0 = 0

The logic circuit is marked with the output and the the output of different gates as below

REG3 0 1 0 DO 00 QO 0 0 0 DI Q1 0 Qi XOR AND 2 0 0 0 0 0 D2 Q2 Q2 0 XOR2 clk clock

So now, D0 = 1, D1 = 0, D2 =0

So when the clock comes, the output will become Q0 = D0 =1, Q1 = D1 = 0, Q2 = D2 = 0. So the next state is Q2 = 0, Q1 = 0, Q0 = 1. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 0, Q1 = 0, Q0 = 1

The logic circuit is marked with the output and the the output of different gates as below

REG3 1 0 1 DO 00 Qo INV 1 1 0 DI 01 0 QI XORZ AND2 0 0 0 D2 0 02 Q2 0 XORZ clk clock

So now, D0 = 0, D1 = 1, D2 =0

So when the clock comes, the output will become Q0 = D0 =0, Q1 = D1 = 1, Q2 = D2 = 0. So the next state is Q2 = 0, Q1 = 1, Q0 = 0. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 0, Q1 = 1, Q0 = 0

The logic circuit is marked with the output and the the output of different gates as below

REG3 0 1 0 DO 00 QO 0 1 1 DI 01 1 Q1 XOR AND 0 1 0 0 D2 Q2 Q2 0 XOR2 clk clock

So now, D0 = 1, D1 = 1, D2 =0

So when the clock comes, the output will become Q0 = D0 =1, Q1 = D1 = 1, Q2 = D2 = 0. So the next state is Q2 = 0, Q1 = 1, Q0 = 1. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 0, Q1 = 1, Q0 = 1

The logic circuit is marked with the output and the the output of different gates as below

REG3 1. 0 1 DO 00 Qo 0 DI Q1 1 Q1 AND2 1 1 0 D2 Q2 Q2 0 XOR2 clk clock

So now, D0 = 0, D1 = 0, D2 = 1

So when the clock comes, the output will become Q0 = D0 =0, Q1 = D1 = 0, Q2 = D2 = 1. So the next state is Q2 = 1, Q1 = 0, Q0 = 0. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 1, Q1 = 0, Q0 = 0

The logic circuit is marked with the output and the the output of different gates as below

REG3 0 0 DO 00 Qo INV 0 0 0 DI 01 Q1 0 XOR 0 AND2 0 0 1 1 D2 Q2 Q2 1 XOR2 clk clock

So now, D0 = 1, D1 = 0, D2 = 1

So when the clock comes, the output will become Q0 = D0 =1, Q1 = D1 = 0, Q2 = D2 = 1. So the next state is Q2 = 1, Q1 = 0, Q0 = 1. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 1, Q1 = 0, Q0 = 1

The logic circuit is marked with the output and the the output of different gates as below

REG3 0 1 DO 00 QO 1 1 0 0 DI 01 Q1 XORZ 1 AND 2 0 0 1 1 1 D2 Q2 Q2 XORZ clk clock

So now, D0 = 0, D1 = 1, D2 = 1

So when the clock comes, the output will become Q0 = D0 =0, Q1 = D1 = 1, Q2 = D2 = 1. So the next state is Q2 = 1, Q1 = 1, Q0 = 0. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 1, Q1 = 1, Q0 = 0

The logic circuit is marked with the output and the the output of different gates as below

REG3 0 1 0 DO 00 Q0 0 1 1 DI 1 01 Qi XORZ 0 ANO2 0 1 1 1 1 D2 Q2 02 XOR2 clk clock

So now, D0 = 1, D1 = 1, D2 = 1

So when the clock comes, the output will become Q0 = D0 =1, Q1 = D1 = 1, Q2 = D2 = 1. So the next state is Q2 = 1, Q1 = 1, Q0 = 1. The next state of a D flip flop is the content given to the D pin

When the present state is Q2 = 1, Q1 = 1, Q0 = 1

The logic circuit is marked with the output and the the output of different gates as below

REG3 0 DO 00 QO 1 0 1 DI 01 Q1 XORZ 1 AND 2 1 1 0 1 D2 Q2 Q2 XORZ cik clock

So now, D0 = 0, D1 = 0, D2 = 0

So when the clock comes, the output will become Q0 = D0 =0, Q1 = D1 = 0, Q2 = D2 = 0. So the next state is Q2 = 0, Q1 = 0, Q0 = 0. The next state of a D flip flop is the content given to the D pin

So the table can be filled as

Present State Next State Q2 Q1 QO D2 D1 DO 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 1 i 1 1

0 0
Add a comment
Know the answer?
Add Answer to:
Also explain in words what this means. Assuming that Q2 Q1 and Q0 are LEDs from...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • The following is an equivalent way of creating the circuit above. Below is the truth table...

    The following is an equivalent way of creating the circuit above. Below is the truth table Q2, Q1, and Q0 are LED outputs from left to right respectively and D2, D1, and D0 are switches from left to right respectively Answer the following questions: 1. What signal(s) represent the present state and next state of the circuit? 2. Sketch a Finite State Machine diagram of the circuit (Be sure to show inputs and outputs). 3. Describe the high-level behavior of...

  • The following three images accompany one another. The second image is another version of the first...

    The following three images accompany one another. The second image is another version of the first which we are using in the example. How does image 4 change the function of the circuit (an input, 'a', has been added that logically influences the next state bits)?? Fill out the truth table to show the change. Note: Q2, Q1, and Q0 are LED outputs from left to right respectively. D2, D1, and D0 are switches from left to right respectively. 'a'...

  • What is the function of this circuit? It is a sequential circuit with no external inputs....

    What is the function of this circuit? It is a sequential circuit with no external inputs. Draw a schematic using the Flip-Flop diagram below that performs the task it is intended to. The design will eventually be programmed to an FPGA board. REG3 DO 00 QO DI 01 101 XORZ AND2 02 02 Q2 XOR2 cik clock D[2] D[1] D[O] D Flip-Flop Flip-Flop Flip-Flop sw_in en sw_in sw_in clock clock clock Q[2] Q[1] Q[o]

  • Design a 3- bit Multipurpose Register. The register utilizes 3 "D" type flip flops with outputs...

    Design a 3- bit Multipurpose Register. The register utilizes 3 "D" type flip flops with outputs Q0, Q1, Q2. The Registers has a synchronous clock input(CLK) that clocks all 3 flip flops on its positive edge The Registers has an asynchronous clear input(CLR' ) that sets all flip flops to "0" when active low. The Register has 2 select inputs, S0 and S1 that selects the functions as folows: S1 = 0, 0, 1, 1 and S0 = 0,1,0,1 and...

  • Problem 7. Consider the 74x194 4-bit bidirectional universal shift register shown below Determine the operation of...

    Problem 7. Consider the 74x194 4-bit bidirectional universal shift register shown below Determine the operation of this circuit by filling out the table. Assume that the register is cleared initially as indicated by the first row in the table, and then connected to +5V (before time t), as shown in schematic. Also assume that t 'is that time at which a positive edge occurs in the input signal 'clock'. Si and S0 inputs (given) are used to switch between modes...

  • Please help Q15. A watch can display one of four items: Time, Alarm, Stopwatch or Date, controlled by two signals Q1 and Q0 (00 time, 01 alarm, 10 stopwatch, 11date). Assume Q1 and Q0 control an N...

    Please help Q15. A watch can display one of four items: Time, Alarm, Stopwatch or Date, controlled by two signals Q1 and Q0 (00 time, 01 alarm, 10 stopwatch, 11date). Assume Q1 and Q0 control an N-bit MUX that passes the correct register to the display. Pressing a button B (sets B-1) sequences the display to the next item, releasing the button resets B-0 and the display remains stable. For example, if the current displayed item is the date the...

  • The task is to design a two-bit controlled counter which has two counting bits (Q2, Q1), has one control input C1, and a...

    The task is to design a two-bit controlled counter which has two counting bits (Q2, Q1), has one control input C1, and also two extra outputs, one indicating overflow, the other underflow. When C1=0 the counter counts up by 2s; i.e. 0 becomes 2, 1 becomes 3. In this mode the values 2 and 3 go to the overflow state. When the control input C1=1, the counter counts down by 2s, i.e. 3 becomes 1, and 2 becomes 0, and...

  • Design a counter to count-up from 2 to 5 using 3 D Flip-Flops similar to the...

    Design a counter to count-up from 2 to 5 using 3 D Flip-Flops similar to the following sample: Important Steps: After you simplify D2, D1 and DO by kmap Have a piece of paper to draw it then open iCircuit to design it using BCD If it works well as a counter, copy the design from iCircuit and paste it here. 3-Bit Counter Using D Flip-Flop: The State Equation of D Flip-Flop: Q(t+1)=D(t) => Dn=An Count Up From 3 To...

  • I am making a 4-bit universal shift register that can perform right shift, left shift, and...

    I am making a 4-bit universal shift register that can perform right shift, left shift, and parallel loading using 4-to-1 multiplexers in VHDL. I keep getting red lines for u3, u2, u1, u0. The error says the following below. What is wrong with my code? How can I fix it? librarviees, use ieee.std_logic_1164.all; entity uni shift.reg.is porti 1 : in std. Jogis vector (3 downto.0); I, w, clock : in std logici 9: buffer std. Jogis vector (3 downto 0));...

  • Basically it is asking to draw the state machine using the D-flipflops and the ICs provided....

    Basically it is asking to draw the state machine using the D-flipflops and the ICs provided. 6.1.4 Simulation Draw the the elevator controller. You must use the ICs listed for this laboratory, i.e., you will need bubble-to-bubble logic to implement the OR functions. Connect the CLK inputs of the flip-flops to a CLOCK signal, and the asynchronous CLR inputs to an active low RESET signal. 25 The sequence of commands to be applied for simulating the elevator controller is (starting...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT