Question

Please write in MIPS assembly

Write a simple code demonstrating the effects of enabling/disabling (1) Branch Target Buffer (2) Delay slot on CPI, number of clock cycles taken, stalls and overall efficiency. Support your discussion with screenshots of the pipeline

Answer 1

BRANCH TARGET BUFFER

• BPB: Tag + Prediction
• BTB: Tag + prediction + next deal with
• Now we predict and “precompute” department final results and goal deal with for the duration of IF
– Of direction more pricey
– Can nonetheless be related to cache line (UltraSparc)
– applied in a sincere manner in Pentium; not so trustworthy in Pentium seasoned (see later)
– Decoupling of BPB and BTB in power pc and dad-8000

branch goal Buffer

department prediction buffers include prediction about whether or not the subsequent department might be taken (T) or no longer(NT), but it does not deliver the target laptop cost. Adepartment goal Buffer (BTB) does this.Instr deal with predicted laptop BTB is a cache that holds
(instr addr, expected laptop)
for each taken branch
The manage unit looks up the department goal buffer in the course of the “F” section The goal laptop is determined out even before it's miles acknowledged to be a department preparation.
BTB hit and pass over
(BTB Hit) Implements 0-cycle branches
(BTB miss) target computer is computed and entered into the target buffer.
Instr cope with anticipated computer
BTB is controlled (by the control unit) as a ordinary
cache. With a larger BTB there are fewer misses and the overall performance improves. Predication
Predication mitigates the hassle of handling conditional branches in pipelined processors.

If
then
else
quit if
If branch to L1
do this;
branch to L2
L1: do that
L2: go out
the usage of predication, we can translate it to every education is carried out while a predicate is true. every education enters the pipeline, but consequences are suppressed if the predicate is false. Predication eliminates branch prediction logic, and allows better bundling of instructions, and now and again higher parallelism. however it wishes more area in instructions.

Predication is used in Intel’s IA-sixty four structure, ARM and some more recent processors

if (R1==0) { BNEZ R1, LL
R2 = R3 upload R2, R3, R0
R4 = R5 upload R4, R5, R0
} else { J NN
R6 = R7 LL: upload R6, R7, R0
R8 = R9 upload R8, R9, R0
} NN:
CMOVZ R2, R3, R1 (conditional circulate: if R1=zero then R2=R3)
CMOVZ R4, R5, R1 (conditional move: if R1=0 then R4=R5)
CMOVN R6, R7, R1 (conditional pass: if R1≠0 then R6=R7)
CMOVN R8, R9, R1 (conditional move: if R1≠zero then R8=R9)

if (R1 == R2) { CMEQ R1, R2, P2, P3
R3 = R4 {if R1=R2 then set P2 else set P3)
} else { upload R3, R4, R0
R5 = R6 upload R5, R6, R0
}
practise stage Parallelism
instruction streams are inherently sequential. but superscalar processors are capable of manage a couple of
instruction streams in parallel. to make use of the available parallelism, it's far critical to take a look at techniques for extracting coaching level Parallelism   Superscalar processors rely on ILP for speedup.
Programm Superscalar Processing
instr 1 2 three four 5 6 7 eight 9
1(integer) F D X M W
2 (FP) F D X M W
three (integer) F D X M W
4 (FP) F D X M W
five F D X M W
6 F D X M W
If N commands are issued in keeping with cycle then the precise CPI is 1/N. however, the probability of risks
increases, and it makes the CPI decrease than 1/N. as an instance, by scheduling more than one unrelated
commands in parallel, ILP improves, and the instruction throughput also improves. ILP can be progressed at run time, or at compile time. Run time techniques of bundling unrelated commands
depend on the manage unit, and will increase the cost of the device. Very big coaching word (VLIW) Processors In VLIW, the compiler packages some of operations from the education circulation intoone big instruction word.

preparation flow.

EPIC makes use of this concept inside the IA-64 specs.
Integer integer FP FP reminiscence reminiscence branch hardware speculation
Superscalar machines often continue to be under-applied.
hardware hypothesis facilitates enhance the utilization of
a couple of issue processors, and ends in higher speedup.
Speculative Execution fi
Execute codes before it's far acknowledged that it will be needed.
agenda instructions primarily based on speculation
store the bring about a Re-Order Buffer (ROB)
dedicate the results when Programm will correct

instance 1
even = 0; unusual= zero; i=0;
at the same time as (i < N) {
k := i*i
if (i/2*2 == i) even = even + k
else odd = odd + k
i= i+1
}
The Strategy
To improve ILP using speculation, until the outcome of branch is known, evaluate both (even + k) and (odd
+ k) possibly in parallel, on a two-issue machine, and save them in ROB Problems and Solutions
What if a speculatively executed instruction causes an exception and the speculation turns out to be false It is counterproductive! Consider this:
if (x > 0) z = y / x;
assume x = 0. the program speculatively executes y/x inflicting an exception! This results in the failure of a
correct application! a hard and fast of repute bits referred to as poison bits are connected to result registers. Poison bits are set by means of speculative instructions after they reason exceptions exception handling is disabled. The poison bits motive an exception whilst the speculation is correct.
Compiler help for higher ILP
Loop Unrolling
take into account the subsequent application on the MIPS processor.
loop: R1 := M[i]; 1
R2 := R1+99; 3
M[i] := R2; five
i := i-1; 6
if (i ≠ zero) then goto loop 8
branch postpone slot nine If the branch penalty is 1 cycle, then every new release of the loop takes 9 cycles. Unrolling of the loop unfolds extra parallelism.
N iterations N/4 iterations
The Unrolled Loop
before optimization After Optimization
loop: R1 := M[i]; loop: R1:= M[i];
R2 := R1+ninety nine; R3:= M[i-1];
M[i] := R2; R5:= M[i-2];
R3 := M[i-1]; R7:= M[i-3];
R4 := R3+99; R2:= R1+99;
M[i-1] := R4; R4:= R3+99
R5 := M[i-2]; R6:= R5+ninety nine
R6 := R5+99; R8:= R7+99
M[i-2] := R6; M[i]:= R2
R7 := M[i-3]; M[i-1]:=R4
R8 := R7+99; M[i-2]:=R6
M[i-3] := R8; M[i-3]:=R8
i := i - 4; i:= i - four
if (i≠0) the goto loop; if (i≠zero) the goto loop;
Estimate the performance improvement now.
Branches might also marginally degrade performance.
smooth to schedule on superscalar architectures.