Translate each of the following pseudo-instructions into MIPS
instructions. You should Produce a minimal sequence of MIPS
instructions to accomplish the required computation.
(8 Points)
1) bgt $t1, 100, Label # bgt means branch if greater than 2) ble
$s2, 10, Next # ble means branch if less than or equal 3) ror $s0,
$s4, 7 # ror means rotate right $s4 by 7 bits and store the result
in $s0 4) neg $s5, $s4 # $s5 will have the negative value of
$s4
[B] Consider the following high-level piece of code: (8
Points)
if ((a > b) || (b > c)) then
{d = 1;}
1) Translate the above code into MIPS assembly instructions
assuming that variables a, b, c, and d are stored in the following
registers $s0, $s1, $s2, and $s3, respectively. Also, assume that
only signed 32-bit integers are used.
2) Now, translate the above code into MIPS assembly instructions
assuming that the addresses of the variables a, b, c, and d are
stored in the following registers $s0, $s1, $s2, and $s3,
respectively. Also, assume that only signed 32-bit integers are
used.
4
Question 2 (14 Points)
[A] Suppose that you are requested to improve the MIPS architecture
by increasing the number of registers from 32 to 64 registers. Do
you think that this would be possible? Justify your answer. If your
answer is “yes”, show how you will do it. (Full credit will be
given for the detailed and perfect answer). (4 Points)
[B] Covert the following machine language codes into their
corresponding MIPS assembly language instructions. Express the
immediate values in decimal. (Show all your steps and calculations
to get full credit) (6 Points)
Machine code1: 00110001000100011000011101100101
Machine code2: 00000000000010010100101010000000
Machine code3: 10001101000010010000000000000000
Machine code4: 00000010110000000000000000001000
[C] Consider an array B with size “n”. Assume that the array’s base
address is stored in register $s0 and its size “n” is stored in
register $s1. Write the MIPS assembly instructions for the
following fragment of high-level code: (4 Points)
k=0;
for (j=0; j < n -1 ; j++)
if ( B[j]==B[j+1]) then k++;
1. bgt $t1, 100, Label # bgt means branch if greater than
Equivalent MIPS code
slti $at,$t1,100
beq $at,$0,Label
2. ble $s2, 10, Next # ble means branch if less than or equal
beq $s2,10,Next
slti $at,$s2,10
bneq $at,$0,Next
3. ror $s0, $s4, 7 # ror means rotate right $s4 by 7 bits and store the result in $s0
srl $t0,$s4,7
sll $t1,$s4,25
or $s0,$t0,$t1
4. neg $s5, $s4 # $s5 will have the negative value of $s4
sub $s5,$zero,$s4
B)
if ((a > b) || (b > c))
then
{d = 1;}
a=s0
b=s1
c=s2
d=s3
slt $at,$s1,$s0
bneq $at,$0,L1
slt $at,$s2,$s1
bneq $at,$0,L1
L1: li $s3,1
Translate each of the following pseudo-instructions into MIPS instructions. You should Produce a minimal sequence of...
Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Register allocations - i $s0 - j $s1 - base of A[] $s2 - base of B[] $s3 2) A[3] = B[i] + B[j]; 3) i = 0; while (j != A[i]) { i++; }
2.9 5 $2.2, 2.3> Translate the following C code to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words: fAlBg
Using beq only, not bge! Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers $s0, $s1, $t0, and $t1, respectively. Also, assume that register $s2 holds the base address of the integer array D. Comments are required. for(i=1; i<a; i++) for(j=1; j<b; j++) D[2*j] = i + j;
C to MIPS Conversion C variable h i j k x int a[] or &a[0] MIPS register replacement $s0 $s1 $s2 $s3 $s4 $a0 Translate to MIPS. DO NOT USE pseudo MIPS instructions (e.g., BGE). Answer MUST use true 32-bit MIPS instructions: if(j < k ) a[j] = 1; else j = a[j];
For C to MIPS Conversion C variable h i j k x int a[] or &a[0] MIPS register replacement $s0 $s1 $s2 $s3 $s4 $a0 Translate to MIPS. No credit for pseudo-MIPS instructions (e.g., BGE). The answer MUST use true 32-bit MIPS instructions: if(j < k ) a[j] = 1; else j = a[j];
C to MIPS Conversion C variable h i j k x int a[] or &a[0] MIPS register replacement $s0 $s1 $s2 $s3 $s4 $a0 Translate to MIPS. DO NOT USE pseudo MIPS instructions (e.g., BGE). Answer MUST use true 32-bit MIPS instructions: Note that all variables (h,i,j,x,a[]) are 32-bit signed integers. while ( h < 3 ) { a[j++]= 0; x = i >> 3; }
IN MIPS AND MUST RUN IN QTSPIM
Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i and j are stored in registers Ss0, Ss1, St0 and Stl, respectively. Also assume that register Ss2 holds the base address of the array D. for (i=0; i<a; itt) for (i-0j<b:jt+)
7. Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a,b, i and j are in registers Ss0, Ss1, St0, and St1, respectively. Also, assume that register SS2 holds the base address of the array D. for(i-0; i<a; i++) for(j=0 ; j<b; j++)
Translate the following C code to MIPS assembly. Assume that the values of a, b, i, and j are in registers $s0, $s1, $t0, and $t1, respectively. Also assume that $s2 holds the base address of the array D. for (i = 0: i < a: i++) for (j = 0: j < b: j++) D[2 * j] = i + j;
The relative time ratings of exercises are shown in square brackets after each exercise number. On average, an exercise rated [10] will take you twice as long as one rated [5]. Sections of the text that should be read before attempting an exercise will be given in angled brackets; for example, <1.3> means you should have read Section 1.3, Under the Covers, to help you solve this exercise. 2.1 [5] For the following C statement, what is the corresponding MIPS...