Question

reset 1 silso operation x x Cleor (load all o's). - Maintain preset value Parallel lood 1 0 shift Right 1 1 Shift left 0 o shr_in I3 I2 I4 IO shl_int SA write the and Q3 Q2 QI do TIT a structural Sistem. Verilog module for multifunction register by using wil multiplexess. synchronously resettable o flip flops.

Answer 1

module MSR(Q,I,clk,reset,s,SHRIN,SHLIN);

wire [3:0] w;

input [3:0]I;

input [1:0]s ;

input clk ;

input reset,SHRIN,SHLIN;

output [3:0]Q;

reg [27:0] count = 0;

//MUX modual calling

mux_4_1 m1(w[0],s[1],s[0],Q[1],SHLIN,I[0],Q[0]);

mux_4_1 m2(w[1],s[1],s[0],Q[2],Q[0],I[1],Q[1]);

mux_4_1 m3(w[2],s[1],s[0],Q[3],Q[1],I[2],Q[2]);

mux_4_1 m4(w[3],s[1],s[0],SHRIN,Q[2],I[3],Q[3]);

//D flip flop modulE calling

D_FF d1(Q[0],w[0],clk,reset);

D_FF d2(Q[1],w[1],clk,reset);

D_FF d3(Q[2],w[2],clk,reset);

D_FF d4(Q[3],w[3],clk,reset);

//increment count on every clock

endmodule

//sub module for D flip flop

module D_FF(q,d,clk,reset);

output reg q;

input d,clk,reset;

always@(posedge clk)

if (reset == 1'b1)

q<=1'b0;

else q<=d;

endmodule



//sub module for 4x1 MUX

module mux_4_1(y,s1,s0,i3,i2,i1,i0);
output reg y;

input i3,i2,i1,i0;

input s1,s0;

always@(s1,s0,i3,i2,i1,i0)

begin if (s0==0 & s1==0)

y=i0;

else if (s0==0 & s1==1)

y=i1;

else if (s0==1 & s1==0)

y=i2;

else if (s0==1 & s1==1)

y=i3;

end endmodule