Question

[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits, and IR is 4 bits. Give the sequence of microoperations required to implement the Execute cycle (Fetch cycle is given below) for the above STA (x)+ instruction. Your solution should result in exactly 8 microoperations. Assume PC is currently pointing to the STA (x)+ instruction and only PC and AC have the capability to increment/decrement itself ALU TEMP AC Internal Data Bus IR PC MDR MAR Internal control signals To/from memory and I/O devices CU External control signals Fetch Cycle Step 1: MAR <- PC; Step 2: MDR <M(MAR), PC <- PC+1 Step 3: IR <MDRopcode, MAR<- MDRaddress ; Read inst. & increment PC

Answer 1