Question

re V(H) (10).pdf WA 2 /9 150%. 66 Canonical and Standara rors Fill in the truth table below Draw the minimized gate level design for Z (Only use NAND and NOT gates). How many transistors would it take to implement this using standard CMOS? Z (A.B.C.D)- 0, 1, 2, 8, 10 ABCD How could a NOT gate be built with only a NAN gate? 1 0 1 1 0 1 1 1 1 1 1 0 source w 1 1 1 1 1 1 1 1 1 Course Hero.c Use a K-map to minimize Z. Write down minimized Boolean Equation. 1 1 01 1 1 1 1 11 1 TR

Answer 1

2=MO, l, 2,8110 4-Marfable 13 C K-Map A O AB 1으 11 3 1 C (V 13 I4 2 1 1 11 1 0 O 0 Z BD+ ÃBC C A O A NOT gake NAND gate 1 D C BB aD+ ABC A.B A N- O C OO