Question

3.3 Design a 2nd-order (-2 poles) LPF that cuts off at 200Hz. a. Cascade two, 1" order sections, each cutting off at 200Hz. Simulate the network with SPICE. b. Cascade two, 1 order sections, ench cutting off at 200Hz, but place a non-inverting buffer between the two sections. Simulate the network with SPICE. c. Compare the responses of a. and b. and explain the differences (if any). Analysis of the two networks will help explain the behaviors.

Answer 1

The problem is solved below.

feel free o ask your doubts in the comment section. please give up vote.

The cut off frequency of the low pass filter is given by f=1/(2*pi*R*C)....where pi=3.141; R and C are the resistor and capacitor values used in the design.

we know f=200 hz.... then take R=10 Kohms and find out the value of the capacitance C... where C=1/(2*pi*R*f)

so you get C=79.5 nano F.

now spice simulation as follows........

(a) cascade of two stages of LPF's

Simulate Tools Window Help D & G 8 20 21 2 3 = = 8 BỀ 8 } + 3 PM 0 0 EE7 Aa p File Edit Hierarchy View L BE ET Draft2 Draft2 Draft2 O x Vn003) OdB -7dB -14dB- -21dB -28dB- -35dB- 42dB- 49dB -56dB -63dB -70dB+ 1Hz 10HZ 100Hz 1 KHZ 10KHz Draft2 x V2 10k 79.5n 79.5n .ac dASbo 1 10k

(b) buffer placed between two stages....

Simulate Tools Window Help D & G 8 20 21 2 3 = = 8 BỀ 8 } + 3 PM 0 0 EE7 Aa p Eile Edit Hierarchy View L BE ET Draft2 Draft2 Draft2 V(n004) . .. OdB -7dB ---------........ -14dB -21dB- -28dB- -35dB 42dB- 49dB- -56dB- -63dB |-70dB 1Hz 10Hz 100Hz 1KHz 10KHz Draft2 Do x R1 vi 10k OPO7 10k 79.5n 79.5n ac decido 1 10k

(c) comparing (a) and (b)

NOTE: BLUE line represents cascading without buffer , GREEN line represents cascade with buffer.

2929 + 3 YDEE Ag.go Vin004) Eile View Plot Settings Simulation Tools Window Help SA TOQQA036% Draft2 Draft2 Draft2 V(n009) OdB- -7dB- -14dB- -21dB- -28dB- -35dB- 42dB 49dB -56dB -63dB |-70dB 1Hz 100Hz 1KHz 10KHz Draft2 -10 R2 R1 NU1 R3 R4 opoz 10k v1 10k C2 V2 10k c3 10k 79.5n 79.5n 79.5n .ac de 900 1 10k ;ac decido 1 10k
By comparing both (a) and (b)

if you observe both in (a) the input resistance of stage-2 is coming in parallel with the capacitor in stage-1 and it is called loading. Due to this we can see that the cut off is coming before 200 hz. but in (b) since we place buffer between two stages, there was no loading occurs and our design is perfectly worked.

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