
Ignore PSpice Simulation Design the MOSFET current mirror shown in Figure 2 to replicate a 1...
Ignore PSpice Simulation
Design the BJT current mirror shown in Figure 1 to replicate a 1 mA reference current at the collector of 02. Assume a scale current of 6.7 fA, V 74 V, and B-200. 1. Determine Ri such that IREF- 1 mA is the current, Ic, flowing into the collector of Qi 2. Calculate Io/IREF, where Io- Ic2. 3. Simulate the circuit in Figure 1 in PSpice. Use the SEDRA_LIB library for the Q2N3904 and enter the appropriate...
1. Design the common source amplifier shown in Figure 1 with Ip- 1 mA and Vo 5 V Determine V2 and Ri. The MOSFET characteristics are V-50 V, k-0.093 A/V, gate-to- drain capacitance, Cd 40 pF, and Vi 1.1 V. (For PSpice simulations, use parameters: VTO. 1.1 LAMBDA-002 KP-0.093 CGDO-4E-7 w=100u L-I00u for the 2N7000 MOSFET.) a. Determine the gain and gm of the circuit b. Determine the low-frequency (high-pass response) poles of the common-source amplifier due to the coupling...
1. Consider the following current mirror combination, where all transistors have the same kn'(W/L) = kp'(W/L) = 2mA/V2, and VTN-1У, VTP--1V. It is also given that VDD1-10V, VDD2-8V. Remember that for saturation the drain current is given by IDー½ k,"(W/L) (VGS-Yn)" for NMOS and ID ½ kp"(WL) (VGS-V,»)2 for PMOS. You can ignore the channel modulation for all transistors. (a) Find the value of R so that I.-1mA. (b) Are transistors Q1, Q2, Q3 in saturation? (c) What is the...
4) Consider the MOSFET differential amplifier shown below, with Io-2 mA, and RL- 10 kS2, Rss-100 k2, VDD- +8V and Vss--8V. The NMOS transistors in the circuit are nominally identical, with kn 2 mA/V2, VTn 1.0 V and ro 100 k2. The PMoS transistors in the circuit are nominally identical, with kp 2 mA/V2, [VTpl 1.0 V and ro 100 kΩ M3 M4 0 M1 M2 a) First consider the DC bias point. Assuming that the current mirror requires at...
An analogue amplifier circuit is shown in Figure 1 below. VDD Q5 15V JL - Vout Irer RI Vina JET T7T Figure 1 Integrated amplifier circuit. Circuit Data: Vpp = 15 V, IREF = I1 = I2 = 1.0 mA Transistor Data: Q1: NMOS, un Cox = 80 A/V?, W/L = 100 um/0.8 um, Vtn = 0.8 V, L = 0.10 um/V Q2: NPN BJT, B = 100, Vbe = 0.7 V, VA = 150 V Q3, Q4: NMOS, un...
R, Figure P7.49 .50 Figure P7.50 shows a current source realized using a current mirror with two matched transistors Q, and o, . Two equal resistances R, are inserted in the source leads to increase the output resistance of the current source. If Q, is operating at gm 1 mA/V and has VA-= 10 V, and if the maximum allowed de voltage drop across R, is 0.3 V, what is the maximum avail- able output resistance of the current source?...
5. You are given a MOSFET biased as shown in the figure. i) Sketch the drain current Ip when Vo is ramped up from 0V to 3 V in a log scale. log(ID ↑ I, 2 0 ) The MOSFET has switched through different operation regions (inear, saturation, subthreshold) during the ramp-up ii) The MOSFET has swit Label the different regions in the graph as you plot the curve above. iii) In dicate the values Vo's that mark the different...
) The current-mirror circuit shown in Figure 3 utilizes pnp transistors having Isl 10-5A and/s2-2x10-5A for transistors Q1 and Q2 respectively and for both transistors a β 50, and |Val 10 V to source a current at Vo.It is required to design the circuit to provide an output current oflo= 1 mA at Vo = 2 V. What values of REF and R are needed? 0i 02 /REF lo
) The current-mirror circuit shown in Figure 3 utilizes pnp transistors...
Problem 10: Consider the differential stage biased by current mirror and loaded with capacitor. MOSFET parametes: Vr-1 V; VA-; (W/L)*kn-2 mA/V; negligible internal capacitances. 5V 8k 10k 5n Vout 5V Find 1. 2. 3. DC voltage at the output; Low frequency small signal voltage gain Vout/Vin; High frequency 3 dB cutoff.
Problem 10: Consider the differential stage biased by current mirror and loaded with capacitor. MOSFET parametes: Vr-1 V; VA-; (W/L)*kn-2 mA/V; negligible internal capacitances. 5V 8k 10k 5n Vout...
29. Identify the type of third stage amplifier: a) inverting amplifier; b) differential amplifier with passi load; c) differential amplifier with current mirror load; d) emitter follower; e) none of above; 30. The Vsg of Q5 should be: a)-1V, b)-0.85% c) 0.65% d)0.85% env 31. To obtain IREF-30μΑ , the value of R should be: a)250ohm; b)25Kohm; c)250Kohm; d)2.5Mohm; e 5Mohm. network is composed by 4 identical phase shifter. The phase shift of each phase shifter in degree should be...