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For a. PR is equal to 4. And the order of b and c is reversed
4. Now consider the timer register podcast. a. Disable timer overflow interrupts and set PR to equal the value you calculated in question 1. Set all other bits to 0. What value is written to TSCR2 to accomplish this? b. What value is written to TIE to enable an interrupt on c. What value is written to IOS to make channel 1 be IC, d. What value is written to TCTL4 to make the IC on the OC channel, and disable all other interrupts? channel 2 be OC, and all other bits be 0? channel 1 capture rising edges? (Assume all other bits are set to 0.) e. What value is written to TCTL2 to make the OC on channel 2 toggle when an output event occurs? (Assume all other bits are set to 0.) r. What register is accessed to read the IC result?
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Answer #1

Answer: - The timer counter register is a decrementing counter. The timer counter register decrements if the timer is enabled using the timer enable bit in the timer control register. If the core in the cortex A5 MPL Core processor belonging to the timer is in debug state, the counter does not decrement until the core returns to non-debug state. When the timer counter register reaches zero and auto reload mode is enabled. It reloads the values in the timer load register and then decrements from that value.

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