Question

1. i. Design and test a 3-to-8 decoder with active-low outputs using VHDL/HDL. Demonstrate your outputs in the BASYS board. (Note: Capture the pictures of your output and add in in your answer script) ii. Include (screenshot) VHDL codes and .xdc file modification in your answer script. ili. Develop a truth table following your outputs. (Note: You do not need to show step by step procedures, except what were asked in the questions]

Answer 1

3 to 8 de woder:- 3 T 3 to 8 decoder - dec-out fig: Block diagram Input li[a] io ilo] output dec-out dec-out decout del-out decou decout decoul decat [7] [6] [5] (W (3 (2] [o co] 000 001 010 011 100 101 IIIIIII Tillo IOI IIIOII! 1110 III 110 IIII! 10 IIIII 011 IIII! Fig: Truth table VHDL code :- library IEEE) use IEEE, STO-LOGIC-1164. ALL; entity 3 to 8_dec is port (is in Std-logic-vector (a downto o); dec-out: out std-logic-vector (7 downto o)); end 3 to 8-dec, architecture behavioral of 3tos_dec is begin process (i) begin case i is

when "000"=) dec-out <=" 0"; when "001" >> dec-out <= " HOI"; when "010" => dec-out <= "11111011"; when woll" = dec-out <= "11110111"; when "100" => dec-out <= "1110 1111"; when "101" - dec-out <= "11011111"; when "110" => dec-out <= "10111111"; when "ll1" =) dec-out <= 101111111" ; when others ->dec-out <= " "; end casei end process; end behavioral; Test bench code: - library IEEE; use IEEE. STO-LOGIC-1164. ALL; entity t3 tos-dec is end t3tos-dec; architecture behavioral of 3 to8_dec is -- component declaration for unit under test (oot) Component 3to 8-dec port (i: in std_logic_voctor (a downto 0)) decout: out std-logic-vector (7 downto o)); end component; - inputs signal i: std-logic-vector (a downto o), --Outputs signal decout; std-logic-vector (7 downto o);

bogin -- Instantiate the UUT weets 3 to 8 dec port map( i=) i; dec-out =) dec-out Ji -- Stimulus process Slim process: process begin i<= "000", wait for 100ns, i<= 1001"; walt for 100ns; i<=1010", wait for loons; i<= 10l1"; wait for loons; <= "100"; wait for 10ons; i <= "101"; wait for 10onsi ic-"110" ; wait for loons; i <= "111" ; wait for loons; end process) end behavioral;

• In the 3 to 8 decoder the 3 inputs are decoded into 8 outputs(active low).
• 3 inputs are i[2],i[1],i[0] and 8 outputs are dec_out[7] through dec_out[0].
• Based on input combination one among 8 is selected as output.
• Suppose input is 000 then dec_out[7]=0(since active low output is required its 0) is selected as output
• Other combinations are shown in the truth table in the image above with the VHDL codes