Question

(b)(i) Using T flip-flop as main components, design a 3-bit synchronous counter that perform counting as the following sequence 0,2,4,6,1,3,5,7 then repeats (its sequence) [20 marks] (ii) Draw a complete circuit to show how the T flip-flops are interconnected and label it appropriately. Also show how the counter can be asynchronous reset. [5 marks] (iii) Draw a timing diagram for at least four clock cycles [8 marks)

Answer 1

state table:

Present X Y state Z ооо o 1 о 1 со Hooo ONL оо Next state o 1 О 1 оо 1 1 0 o o 1 0 1 1 1 0 1 1 1 1 боо т, т. Т. o1 о 1 1 0 o 1 о 1 1 1 o 1 о 1 1 0 o 1 о 1 1 1 oo 1 01 1 1 0 1 1 1 1

k-maps:

y yz yz yz TY 72 ý 72 72 72 71 71 Tt-1 92 yz 12 - XY

circuit :

.. . Ti ehot Ti eno , , , , * [URIl * * * * - ....... reset 0 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S {0}) . . . .

اااااااا