Question

Type down the code so I can copy it directly please. Dont write on papers or dont provide it as screenshots, only type it please. I will upvote too. Thanks.

Figure 3 shows the connection between a common anode 7-segment display, three switches and an FPGA. Write the VHDL code that can be used to display odd numbers, given as an input using the three switches, on the 7-segment display. In the case of even numbers, display the letter 'E'. FGPA Switshes ALTERA Cyclone V Fig. 3

Answer 1

library ieee;

use ieee.std_logic_1164.all;

entity oddno is

port(a: in std_logic_vector(2 downto 0);

y: out std_logic_vector(6 downto 0));

end oddno;

architecture beh of oddno is

begin

process(a)

begin

case a is

when "000" =>

y<= "0110000"; -- format for show E in seven segment display

when "001" =>   -- odd no.

y<= "1001111";   -- format for show 1 in seven segment display

when "010" =>

y<= "0110000";    -- format for show E in seven segment display

when "011" =>   -- odd no.

y<= "0000110";   -- format for show 3 in seven segment display

when "100" =>

y<= "0110000";    -- format for show E in seven segment display

when "101" =>

y<= "0100100";   -- format for show 5 in seven segment display

when "110" =>

y<= "0110000";   -- format for show E in seven segment display

when "111" =>

y<= "0001111";    -- format for show 7 in seven segment display

when others=>

y<= "0110000";   -- format for show E in seven segment display

end case;

end process;

end beh;