Homework Answers
a. Direct addressing Mode
b.Immediate addressing mode
c.Register Indirect Addressing Mode
d.Immediate addressing mode
e.Displacement Addressing Mode
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Identify the type of addressing mode for the following instructions: A) Load R2,1000 B) Load R2...
Consider the following operations: A B- C The corresponding assembly code instruction list generated by a compiler are 1 load [%r0 +4], %r1 2 load [%r0 + 8], %r2 3 sub %r1, %r2,%r3 4 load [ZrO + 1...
Consider the following operations: A B- C The corresponding assembly code instruction list generated by a compiler are 1 load [%r0 +4], %r1 2 load [%r0 + 8], %r2 3 sub %r1, %r2,%r3 4 load [ZrO + 12], %r4 5 add %r3, %r4 , %r5 6 store %r3, [%r0 + 16] 7 store %r5, [%r0 + 20] a) Identify the potential pipeline hazards. (10 points) b) State if the found hazards can be eliminated and if so propose a scheme...
Question 5 What are the addressing modes of the following assembly instructions? 1) (1 point) LDR...
Question 5 What are the addressing modes of the following assembly instructions? 1) (1 point) LDR R1, R2] A. Immediate mode B. Register mode C. Relative mode D. Indirect mode 2) (1 point) SUB RO, R1, R4 A. Immediate mode B. Index mode C. Register mode D. Indirect mode 3) (1 point) BMI target A. Immediate mode B. Register mode C. Relative mode D. Indirect mode Question 6 Which of the following utility software tools can translate high level language...
mention the type of addressing mode of each line of the given code, URGEEENNT PLEASE CLRA...
mention the type of addressing mode of each line of the given code, URGEEENNT PLEASE CLRA LDAA #$27 LDAB #$5 ABA STAA $8000 STAB $8001 LDX $8000 LDX #$10 LDAA 0,X LDAA 1,X LDAA -2,X STAA -1,SP LDAB 1000,PC
A. For each operand and result within each of the following assembly language instructions categorize each...
A. For each operand and result within each of the following
assembly language instructions categorize each addressing mode
using the 5-types framework of Figure 7.6. Each instruction
will have three answers to be listed.
LOAD R4,
12+R9 ; list modes here in order,
separated by commas (3 answers)
ADD R6, R5,
R4 ; list modes for ADD here (3
answers)
B. What addressing occurs, if any, in the instructions in part
(a) that was not captured in your...
Implement the following statements using MS430 assembly instructions. You may use more than one, ...
Implement the following statements using MS430 assembly instructions. You may use more than one, but you should minimize the number of instructions required. You can use both native and emulated instructions. Use hex notation for all numbers 1. (a) Move the word located in register R14 to R15 (b) Increment the word in R6 by 2. (c) Perform a bitwise ANDing of the word located at address 0x0240 with the datum in R15, placing the results in R15. (d) Rotate...
Q 2. Assuming a 32-bit operating environment, identify the mode of each operand in the following...
Q 2. Assuming a 32-bit operating environment, identify the mode of each operand in the following instructions. (Note: There are two operands in each instruction; identify both modes.) For a memory operand, specify whether it is direct memory mode or register indirect memory mode. Assume that the instructions are in a program also containing the code. .DATA value DWORD ? char BYTE *1. mov value, 100 2. movecx, value 3. mov ah, Oah *4. moveax, (esi] 5. mov [ebx], ecx...
Consider the following. load r1, 16(r2) ; S1 addi r4, r4, r1 : S2 addi r10,...
Consider the following. load r1, 16(r2) ; S1 addi r4, r4, r1 : S2 addi r10, r12, r14 ; S3 bnez r10, target; S4 addi r14, r, r10; S5 store r10, 0(r2); S6 Q. Identify each dependency by type (data, name or control dependency); list the two instructions involved; identify which instruction is dependent; and, if there is one, name the storage location
a) Describe the main techniques used by superscalar processors to achieve a high degree of machine-level parallelism. Consider the following assembly code: I1: LOAD r3 (r1) TO 12: MOVE r4 #1 1...
a) Describe the main techniques used by superscalar processors
to achieve a high degree of machine-level parallelism.
Consider the following assembly code: I1: LOAD r3 (r1) TO 12: MOVE r4 #1 13: ADD r3 r3 r4 I4: LOAD r2 (r2) 15: MOVE r4 #2 I6: MUL r2 r2 r4 17: MUL r3 r3 r2 I8: LOAD r4 (r1) 19: MOVE r1 #3 I10: ADD r4 r4 r1 I11: MUL r3 r3 r4 Using register renaming reorganise the code from the...
4. Study the following example, and determine the addressing mode used in each instruction: .data Arr: .word 10 .word 2...
4. Study the following example, and determine the addressing mode used in each instruction: .data Arr: .word 10 .word 20 .text globl main main la $s0, Arr lw $t0, 0(Ss0) lw St1, 4(Ss0) add St2, $t0, $t1 addi $t2, $t2, 1 sll $t2, $t2, 1
4. Study the following example, and determine the addressing mode used in each instruction: .data Arr: .word 10 .word 20 .text globl main main la $s0, Arr lw $t0, 0(Ss0) lw St1, 4(Ss0) add St2,...
Part 2 (22 pts) .ORIG x3000 LEA R1, STRZ AND R2, R2, #0 LD R4, CHAR...
Part 2 (22 pts) .ORIG x3000 LEA R1, STRZ AND R2, R2, #0 LD R4, CHAR REPEAT LDR R3, R1, #0 BRz FINISH ;Branch to FINISH if the value of R3 is zero ADD R3, R3, R4 BRnp PASS ;Branch to PASS if the value of R3 is positive or negative ADD R2, R2, #1 PASS ADD R1, R1, #1 BR REPEAT ;Branch always to REPEAT FINISH ST R2, COUNT HALT CHAR .FILL xFF91 COUNT .FILL x0000 STRZ .STRINGZ "Hello...
Consider the following operations: A B- C The corresponding assembly code instruction list generated by a compiler are 1 load [%r0 +4], %r1 2 load [%r0 + 8], %r2 3 sub %r1, %r2,%r3 4 load [ZrO + 12], %r4 5 add %r3, %r4 , %r5 6 store %r3, [%r0 + 16] 7 store %r5, [%r0 + 20] a) Identify the potential pipeline hazards. (10 points) b) State if the found hazards can be eliminated and if so propose a scheme...
Question 5 What are the addressing modes of the following assembly instructions? 1) (1 point) LDR R1, R2] A. Immediate mode B. Register mode C. Relative mode D. Indirect mode 2) (1 point) SUB RO, R1, R4 A. Immediate mode B. Index mode C. Register mode D. Indirect mode 3) (1 point) BMI target A. Immediate mode B. Register mode C. Relative mode D. Indirect mode Question 6 Which of the following utility software tools can translate high level language...
A. For each operand and result within each of the following
assembly language instructions categorize each addressing mode
using the 5-types framework of Figure 7.6. Each instruction
will have three answers to be listed.
LOAD R4,
12+R9 ; list modes here in order,
separated by commas (3 answers)
ADD R6, R5,
R4 ; list modes for ADD here (3
answers)
B. What addressing occurs, if any, in the instructions in part
(a) that was not captured in your...
Implement the following statements using MS430 assembly instructions. You may use more than one, but you should minimize the number of instructions required. You can use both native and emulated instructions. Use hex notation for all numbers 1. (a) Move the word located in register R14 to R15 (b) Increment the word in R6 by 2. (c) Perform a bitwise ANDing of the word located at address 0x0240 with the datum in R15, placing the results in R15. (d) Rotate...
Q 2. Assuming a 32-bit operating environment, identify the mode of each operand in the following instructions. (Note: There are two operands in each instruction; identify both modes.) For a memory operand, specify whether it is direct memory mode or register indirect memory mode. Assume that the instructions are in a program also containing the code. .DATA value DWORD ? char BYTE *1. mov value, 100 2. movecx, value 3. mov ah, Oah *4. moveax, (esi] 5. mov [ebx], ecx...
a) Describe the main techniques used by superscalar processors
to achieve a high degree of machine-level parallelism.
Consider the following assembly code: I1: LOAD r3 (r1) TO 12: MOVE r4 #1 13: ADD r3 r3 r4 I4: LOAD r2 (r2) 15: MOVE r4 #2 I6: MUL r2 r2 r4 17: MUL r3 r3 r2 I8: LOAD r4 (r1) 19: MOVE r1 #3 I10: ADD r4 r4 r1 I11: MUL r3 r3 r4 Using register renaming reorganise the code from the...
4. Study the following example, and determine the addressing mode used in each instruction: .data Arr: .word 10 .word 20 .text globl main main la $s0, Arr lw $t0, 0(Ss0) lw St1, 4(Ss0) add St2, $t0, $t1 addi $t2, $t2, 1 sll $t2, $t2, 1
4. Study the following example, and determine the addressing mode used in each instruction: .data Arr: .word 10 .word 20 .text globl main main la $s0, Arr lw $t0, 0(Ss0) lw St1, 4(Ss0) add St2,...
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