Question

Design a memory interface for the 8086, which will provide 256K bytes of SRAM, organized as 128K x 16 bits, starting at address 40000H and using SRAM chips 32K x 8 bit. The SRAM chips have three control signals WR, OE and CS. Use the 74LS138 (3- to-8 decoder) for the implementation of the decoding circuit. The 74LS138 has three control signals G₁, G2A, and G2B.
Q3. (5%) Design a memory interface for the 8086, which will provide 256K bytes of SRAM, organized as 128K x 16 bits, starting at address 40000H and using SRAM chips 32K x 8 bit. The SRAM chips have three control signals WR, OE and Cs. Use the 74LS138 (3- to-8 decoder) for the implementation of the decoding circuit. The 74LS138 has three control signals G1, G2A, and G2B. RCMO G1 G2A G2B YO Y1 C Y2 Y3 - Y4 - Y5 Y6 C Y70 74LS138

Answer 1

Given Size of SRAM 126Kx16. bits Starting address • 4000 H Size of SRAM chips, 32x*8 nember of chips 178 xlk2gchips Step 1 32K X8 1 32xx 16 can be organised as cascading of 2 32xX8_SRAM Chijos Even Bank 45cs of Even bank ODD bank 4 Tes of odd bank słupa Even bank SRAM.) (32) SRAM 3 32x) SRAM-5 (32) SAAM. 7 (32%) Ending odd bank SRAM_2 (32K) SRAM.4. B2K) SRAM 6132x) SRAM. 8132K) Addrexs+ chipsitet Addresa starting

Stop 3 Address decading Table For Attuess decoding book since ax can charse either even en end are placed side side they by Here I choose fren bank Tlemosty. Je HEX Address Binary Middress ATA, A 32XX8 SRAM I stadt 04000 ARABATAG ALS ALGABAR AL-ALAGA A MACAU 0000 OJDD 0000 0000 0000 End IzFFE 000 ) PODNI DINI 12 IND 32kx8 SRAM-Z stast 14000 End 23FFE ODOI 10100 0000 0000 0000 dolo دهم 1111 U10 32kx8 SRAMS Start 24000 0000 0000 0010'01oo 0000 0011 - End 33£EE ODM LHD 1 32KX8 SRAM-7 0000 2000 Start 34000 0011' 01bo 0000 End 43EEE OIDO 0022 111) ܐ ܐܐܐ 110 there of use partial decoding & use Az Alf AB SRAM 1 O 0 0 0 SRAM 3 0 o SRAM 5 SRAM F