Question

2. Design an even parity detection circuit. A parity bit is an error checking mechanism. Your circuit will count the number of 1's in a stream of bits. If the number of l's is even, the circuit turns on an output called y. Assume a single bit at each cycle - call the input x. Do not use an accumulator or counter. Design the even parity detection circuit using J-K flip-flops. Your answer must include: a. The state diagram. b. The state table. c. Simplified equations - use either Boolean algebra or k-maps. d. The final circuit(s). 3. Design a synchronous counter for the sequence 3, 7, 12, 11, 15, 1, 13, 8, 3, ... using a J-K flip flop for the MSB, and T flip-flop for the LSB, and D flip-flops for any remaining state bits.

Answer 1

State Diagram X=0 X- O Even(o)) Y= 1 ODD(1) Y=0 X-1 ve so O b) State Table Present state input Next State Excitation outy To Ko Even o o Even o Even o 1 Odd 1 Odd 1 o Odd 1 Odd 1. 1. Even o x I 1 a) Simplified equations .. k map for To k map for to kmap for Y - HOOA x4 KO X X IXX / 10 x Od J Y = 8.6X 8 h Ko=X To = X d) X- T oy Scanned Genk CamScanner

3 - for the given aequence 3,7,12, 11, 15, 1, 13, 8, 3 ... the State Transition table will be Present State Next State Excitalition 83C829,00 Statuto Is K₂ D₂ Di To OO!! O!!! O x 1 1 0 O! Too I loo loi Tol Till 11 11 0001 OOOL i 101 I lol looo TOOO 0011 -0-0- XOO - XO- 0--0- X X X-XX rod toooth Kwer a Ts Qimo g. Qualo_19@om . .K map to K3 Qo9.6. Pipe Qax.xxx ®, xxx 4 x 2 Q%. x x 44 x x 4 Qax, X, X, X. J3 = 0,+Q2 Кто би б POTEKLA K3=Q29,+Que 1 Kmap for Di Qe Po ,90 9.90, Q., go x Aux 11 Is A Di = Q380+0291 Scanned with Can Dzar3+29,

K map for To 080, Qo QQ0 9,60 09.17 it in To = 830, +88382 ,% OC