Question

i just want the code

Write a module in Verilog HDL that describes a parallel load shift register. The following are the requirements for the shift register • The shift register shifts right by one position at a time The shift register size (in bits) is set by a parameter called WIDTH The shift register has a parallel data bus input for loading a value in parallel. The parallel bus is called datalp. The size of the dataly, bus uses the same parameter WIDTH A separate input called datal.oad controls loading the register. Another input called shEnable shifts the contents of the register by a single position to the right The circuit has a single output called serialQut which is connected to hit 0 of the shift register. The following truth table shows the operation of the shift register cik dataload shEnable datalo Shift register serial Remark (WIDTH-1: 0 WIDTH-1:01 Out 0/ 1X X X XXS-..S SOO No Change 11 XDDDD-1...D D0 Par. Load 1 0 1 XXX OS-1...S,S, SO O O XXX S S So 0 No Change Shift The interface of the circuit is shown below WIDTH Shregserialut datain dataload shEnable Guidelines • It is imperative to initialize the shift register to 0. • Use the concatenation operation to describe the shift • Use the if statement to implement the control of the load and shift operations through the datal.oad and shEnable signals

Answer 1

module ShReg(clk, rst, dataIn, dataLoad, shEnable, serialOut);

parameter WIDTH = n // here n is any number requirement of your bit....

input clk, rst, dataLoad, shEnable;

Input [n:0] dataIn;

output serialOut;

reg [n:0] shift bus ;

always@(posedge clk)

begin

If (rst)

shift bus <= n b'0;

else begin

If ( dataLoad)

begin

shift bus <= dataIn; // parallel data load....

end

else begin

if(shEnable) begin

shift bus <= shift bus >> 1; // right shift by one bit...

serialOut <= shift bus[0]; end

end

end

end

end module