Question

A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides the percentage of executed instructions for each type of instruction. Instruction Executed P ipeline CPU type instructions (%) w/o hazards ALU 29.4 Load 29.7 Store 14.7 Branch 26.2 2 (w/o prediction) 27% of the load instructions are followed by instructions that need the data being loaded, 47% of the branches are actually.not taken, please assume not taken prediction. a) Please determine the overall cycles per instruction (CPI). For this pipelined implementation please use CPI = CPlideal + Stalls b) Delay times of the hardware blocks are provided in the table below. Using these delays and please determine the clock cycle time (cct). Hardware blocks and delay times Hardware block Max. delay Memory read/write 0.50 nsec Register read/write 0.24 nsec Control (at ID stage) 0.33 nsec ALU 0.42 nsec Sign extend 0.11 nsec Once cct is determined, please compute the CPUtime. This is given as follows: CPU time = IC X CPI X cct Where IC, CP/ and cct are instruction count, cycles per instruction, and clock cycle time, respectively.

Answer 1

a)

Pipeline CPL wlo hazards | Instruction | type ALU Load Store Branch instructions (%) 29.4 29.7 14.7 26.2 1 2 (wlo prediction)

I'll refer this table for all that data for part (a).

• 27% of load instructions are followed by instruction that need the data being loaded.

it means 27% of 29.7% instructions need the data being loaded additionally to the load instructions.

so, all instructions which need data to be loaded is (1+0.27)*0.297

stall cycles in Load = 1.27*0.297*1 = 0.37719

• 47% of the branches are actually not taken, and assume not taken prediction.

It means 47% of branch instruction need no stall cycles.

and 53% of branch instruction require stall cycles.

therefore,

stall cycles in Branch = 0.53*0.262*2 = 0.27772

• stall cycles in ALU = 0.294*1 = 0.294
• stall cycles in store = 0.147*1 = 0.147

Total stalls = 0.37719 + 0.27772 + 0.294 + 0.147 = 1.09591

Avg CPI = CPIideal + stalls = 1 + 1.09591 = 2.09591

CPI = 2.09591

b)

Hardware blocks and delay times Hardware block Memory read/write Register read/write Control (at ID stage) ALU Sign extend Max. delay 0.50 nsec 0.24 nsec 0.33 nsec 0.42 nsec 0.11 nsec

we can see delay is maximum in memory read/write block,

therefore, clock cycle time must be greater than or equal to delay at memory read/write block

which is,

cct > 0.50 nsec

hence, cct = 0.50 nsec

CPUtime = IC * CPI * cct

= (12.3*107 ) * 2.09591 * 0.50 nsec

= 12.88985 * 107 nsec

= 128.8985 msec