Question

CHAPTER 6 SYNCHRONOUS SEQUENTIAL CIRCUITS Reset =1/R2 =l, R3 1/R1 # - (c R3x = 1, R1, n = 1, Don . Figure 6.28 State diagram for Example 6.4. Flip-flopy should be set to 1 if the FSM is in state A and w = 1; hence Y; = wy. Flip-flop y should be set to 1 if the present state is B; hence Yz = y2. The derivation of the out- put expressions, which we leave as an exercise for the reader, can also be done by inspection. The preceding discussion deals with the basic principles involved in the design of sequential circuits. Although it is essential to understand these principles, the manual approach used in the examples is difficult and tedious when large circuits are involved. We will now show how CAD tools are used to greatly simplify the design task. 6.4 DESIGN OF FINITE STATE MACHINES USING CAD TOOLS Sophisticated CAD tools are available for finite state machine design, and we introduce them in this section. A rudimentary way of using CAD tools for FSM design could be as follows: The designer employs the manual techniques described previously to derive a circuit that contains flip-flops and logic gates from a state diagram. This circuit is entered inte

could you write a verilog code for figure 6.28 please.

Answer 1

module figures6_28 (clock, Reset, w, R1in, R1out, R2in, R2out, R3in, R3out, Done);

input clock, Reset, w;

output reg R1in, R1out, R2in, R2out, R3in, R3out, Done;

parameter A = 2'b00, B = 2'b01, C = 2'b10;

reg [1:0] state, next_state;

always @ (posedge clock or Reset)
begin

   if (Reset)
       state <= A;
   else
       state <= next_state;
end

always @ (state or w)
begin

   R1in <= 1'b0;
    R1out<= 1'b0;
   R2in <= 1'b0;
   R2out<= 1'b0;
   R3in <= 1'b0;
   R3out<= 1'b0;
   Done <= 1'b0;

   case (state)
       A:   if (w) begin
               next_state    <= B;
               R2out        <= 1'b1;
               R3in       <= 1'b1; end
           else
               next_state   <= A;

       B:   begin    next_state   <= C;
               R1out       <= 1'b1;
               R2in       <= 1'b1; end

       C:   begin   next_state   <= A;
               R3out       <= 1'b1;
               R1in       <= 1'b1;
               Done       <= 1'b1; end

       default:    next_state   <= A;

   endcase

end

endmodule

//Simulated on ModelSim

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