Question

1. a.) The Fibonacci sequence is a famous math construct that is surprisingly often reflected in nature. Its construction is simple, its members are simply the sum of the previous 2 numbers. So it starts like this:0, 1. 1, 2, 3, 5, 8, 13, etc. Create the truth table and Karnaugh map for a circuit that detects members of the sequence between 0 and 15 (since we have 4 input bits). (5 pts) A B C D F ABI 00 01 | 11 | 10 CD 01 10 1 0 0 1 b.) Identify the prime implicants by circling them and indicate their logical expressions below. (5 pts) c) Sketch the resulting circuit using AND, OR and NOT gates. (Exclude any inputs that aren't necessary, if any.) (3 pts) d.) Create a verilog module using an always block (with appropriate sensitivity list) that would perform the same task. Do this part in the lab-you have one hour. Print out your module when finished. (10 pts)

Answer 1

(a)The truth table

F 1111010010000100 0000000011111111

This can be drawn directly by observation. The input number is a fibonnaci number if it is 0, 1, 2, 3, 5, 8, or 13.(indicated in blue). From this the K-Map can be simply drawn and is as follows.

The prime implicants are(as numbered in the figure):

1. A'B'
2. BC'D
3. B'C'D'
4. A'C'D'

Of these, 1,2, and 3 are Essential prime implicants because they are the only ones that cover minterms 3, 13, and 8 respectively.

Since these three together cover all minterms, 4 is not required.

(c)$F=A'B'+BC'D+B'C'D'$

Implementing this using gates we have the following circuit.

The cicuit can be directly drawn using the Logic function.

(d)Implementing the circuit using simple gate level description with sensitivity list

The output waveform for this code is the following which is correct.