Let us assume that processor testing is done by (1)
filling the PC, registers, and data and instruction memories with
some values (you
can choose which values), (2) letting a single instruction execute,
then (3) reading
the PC, memories, and registers. These values are then examined to
determine if
a particular fault is present. Can you design a test (values for
PC, memories, and
registers) that would determine if there is a stuck-at-0 fault on
this signal?
Solution
For testing for a "stuck-at-0" fault on a wire, we require an instruction that puts that wire to a value of 1 and has a different result if the value on the wire is stuck-at-0:
If this signal is stuck-at-0, an instruction that writes to an odd numbered register will end up writing to the even numbered register.
Therefore if we place a value of 0 in R30 and a value of 1 in R31, & then execute
ADD R31, R30, R30
the value of R31 is supposed to be 0. If bit 0 of the Write Register input to the Registers unit is stuck-at-0, the value is written to R30 instead and R31 will be 1
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all the best
Let us assume that processor testing is done by (1) filling the PC, registers, and data...
4.6 When silicon chips are fabricated, defects in materials (eg, silicon) and manufacturing errors can result in defective circuits. A very common defect is for one wire to affect the signal in another. This is called a cross-talk fault. A special class of cross-talk faults is when a signal is connected to a wire that has a constant logical value (eg, a power supply wire). In this case, we have a stuck-at-0 or a stuck- at-l fault, and the affected...
3. Assume the processor data path show below. XE30 Add Add ALU result Shift left 2 RegDst Branch MemRead Instruction (31-26] RegSrc Control ALUOP Mem Write ALUSrc RegWrite PC Instruction (25-21) Read address Instruction (20-16] Instruction [31-0) Instruction instruction (15-11) memory Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers Zero ALU ALU result Read Address data OX OX3) 3x) Write Data data memory Instruction [15-0) 16 32 Sign- extend ALU control...
section 13.6
let us assume the following worst case latencies for the blocks
in our data path, the sum of which yields the execution latency for
lw instruction:
instruction access 2 ns
Register read 1 ns
ALU operation 2 ns
Data cache access 2 ns
Register write back 1 ns
total 8 ns
(13.8 Performance of the single-cycle design Discuss the effects of the following changes in the performance results obtained in Section 13.6: a. Reducing the register access time...
Group Project 1 The Micro-1 Processor Simulation <Micro-1 Computer> Here's the organization of a computer equipped with a Micro-1 processor Memory contains an array of integer cells: int cell[] = new int[CAP]; where CAP is the capacity of memory. Initially this is set to 256. Internally, the Micro-1 processor is equipped with eight 32-bit data/address registers and two 32 bit control registers: PC, the program counter, contains the address of the next instruction to execute. IR, the instruction register, contains...
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