Question

“Annulling” an instruction is defined as preventing the instruction from having any effect without having to flush the instruction from the pipeline. Which of the nine control bits generated by the control unit for the MIPS pipeline should be de-asserted to have the effect of annulling the instruction in the branch delay slot?. Use the minimum number of control bits.

Answer 1

Answer:-

Let's take a look at some strategies that have been proposed for conditional branch prediction. There are two issues: outcome prediction and target prediction. The most important aspect of a branch prediction strategy is accuracy. Higher levels of sophistication in branch prediction strategies lead to higher accuracy.

Branch Direction Prediction

Here are some ideas for branch outcome prediction (or "branch direction prediction"), the problem of predicting whether a conditional branch will be taken or not taken.

• Static branch prediction. Static branch prediction means that the prediction is the same every time a branch is fetched. There are three levels of static branch prediction strategies:
  • Always taken/Always not taken. Every branch is predicted to go a particular way. Implementing an "always not taken" strategy is the simplest thing to do, since it eliminates the need for target prediction. Instructions are fetched and speculatively executed down the not-taken path. The accuracy of this technique is low; however, it can be improved with compiler cooperation.
  • Heuristics depending on the instruction. For instance, a popular strategy is "backward taken/forward not taken." Backward branches are assumed to be loop back edges that are frequently taken, while forward branches are assumed to be frequently not taken. This strategy is more accurate.
  • Hint bits in the ISA. Some ISAs allow conditional branch instructions to include hint bits that let the microarchitecture know which direction the branch is likely to be taken. These hints bits can be set through smart compiler heuristics, or through training in a profiling run of the program. This technique achieves about 90% accuracy in the SPEC CPU integer benchmarks.
• Dynamic branch prediction. Every time a branch is executed, a machine algorithm gives a prediction for the branch. Dynamic branch prediction can predict branches that static branch prediction can't, for instance, loop back edges with fixed trip counts. Let's look at some increasingly complex dynamic branch predictors to see how they achieve high accuracy:
  • Bimodal (or "Smith") predictors. A table of bits, indexed by branch PC, is kept. Each time a branch executes, the corresponding bit is set to 1 if the branch was taken, 0 otherwise. The next time the branch needs to be predicted, the corresponding bit is taken as the prediction. This is like the hint bits in the ISA for static prediction, but the hint bits are learned on-line, without a separate profiling run. Note that this system will predict highly biased branches well, but for instance a loop back edge with a low trip count will be mispredicted twice: once at the loop exit, and once the very next time the back edge is encountered.
  • Bimodal prediction with hyseresis. Instead of keeping a table of bits, we keep a table of two-bit counters that saturate at 3 and 0. When a branch is taken, the corredponding counter is incremented. When the branch is not taken, the counter is decremented. When a branch needs to be predicted, the high bit of the corredponding counter is taken as the prediction. The low bit provides hysteresis, i.e., takes into account the history of the branch beyond just the last time the branch was executed. So a loop back edge will incur only one misprediction at a loop exit.
  • Two-level adaptive branch prediction. A history shift register is kept, either for all branches (global) or for each branch (local). The length of this register is called the history length. As branches are executed, their outcomes (1 for taken, 0 for not taken) are shifted into this register. The register is used to index a table of two-bit saturating counters to do prediction with hysteresis. Once this scheme has gone through a sufficient (small) training period, it can perfectly predict loop back edges with small fixed trip counts. This scheme is highly susceptible to aliasing in which two unrelated branches contend for the same counter, resulting in reduced accuracy. Many ways to address aliasing have been proposed. Two-level branch prediction is present in all modern general-purpose microprocessors. How many table entrie are required for a history length of N?
  • Hybrid branch prediction. Two or more predictors are combined to provide a more accurate estimate. For instance, local and global two-level predictors can be combined, or two global predictors with different history lengths.
  • Other predictors. Neural predictors, predictors based on decision trees, or finite state machines learned off-line, combinations of static and dynamic prediction, etc.