Draw the architecture including buses and the uni- or bi-directional flow of information on the buses for a processor that has the components below. Suggestion: sketch the diagram before drawing your final answer.
a. PC
b. IR that includes an addressing mode and an address or literal operand
c. Memory registers
d. ALU
e. N registers
The Architecture including buses and the flow of information on the buses for a processor is as follows:

The explanation of the above diagram is as follows:
Here AR: Address register, PC: Program counter, DR: Data Register, AC: Accumulator, INPR: Input Register, IR: Instruction Register, TR: Temporary Register, OUTR: Output Register
LD: Load, INR:Increment, CLR: Clear
Read a word from the memory:
The bus is connected to a multiplexer through which we can select different register based on our requirement
For example: If we want to read a word from the memory we shall select Program Counter by selecting S2 S1 S0 as 010 by doing so the entire data from the program counter will be available on the bus.Now, by giving the control signal load to the Address register. The entire data present in the bus will get loaded to the Address Register, as the Address Register is connected to the Memory through the Address bus .The Address at the location given through the Address bus will get selected in the Memory. We can now select S2 S1 S0 as 1 1 1 and by doing so the entire data from the selected location in the Memory will be in the data bus.
Now, by giving a control signal Load to the Instruction register the data present in the bus will be loaded to the Instruction Register. The Instruction Register is connected to a Decoder from which we can determine the addressing mode of the instruction.
Assuming the Instruction to be a Register Direct instruction we can perform the operation
movl var, %eax where var is the content of the memory location
PC -> AR
AR ->Memory
Memory->IR
Taking Input from Keyboard and Display
The input from the keyboard will be stored in the Input register. Then will be transferred to the Accumulator via the ALU then by selecting S2 S1 S0 as 1 0 0 the data will be transferred to the bus .And by giving the control signal Load to the Output Register the data will be transferred to the Output Register. And the Data will be ready to display.
INPR->ALU
ALU->AC
AC->OUTR
Draw the architecture including buses and the uni- or bi-directional flow of information on the buses...