Question

Design a vga checkerboard in vhdl using a 25MHz clock.

Answer 1

SOLUTION:

/* VGA checker board in v h d l with a 25 M H z  input clock.*/

library i e e e;

use i e e e.std_logic_1164.all;

use i e e e.numeric _std.all;

entity VGA_Sync_Pulses is

generic (

g_TOTAL_COLS : integer;

g_TOTAL_ROWS :integer;

g_ACTIVE_COLS :integer;

g_ACTIVE_ROWS : integer

);

port (

i_C l k    : in

std_logic ;

o_HS y n c : out

std_logic;

o_V S y n c :out

    std_logic;

o_col_count : out

std_logic_vector(9 down to 0 );

o_Row_count :out

std_logic_vector(9 down to 0)

);

end entity VGA_Sync_Pulses:

architecture R T L of

VGA_Sync_Pulses is

signal r_Col_count :integer

range o to g_TOTAL_COLS-1:=0;

signal r_Row_count :integer

range 0 to g_TOTAL_ROWS-1:=0;

begin

p_Row_col_count:process

(i_c l k) is

begin

if rising_edge(i_c l k) then

if r_col_count =

g_TOTAL_COLS-1 then

if r_Row_Count=

g_TOTAL_ROWS-1 then

r_row_count <=0;

else

r_row_count<=

r_Row_count +1;

end if;

r_col_count <=0;

else

r_col_count +1;

end if;

end if;

end process p_row_col_count;

o_H Sync <= '1' when

r_col_Count <g_ACTIVE_COLS

else '0' ;

o_V S y n c <='1' when

r_Row_count < g_ACTIVE_ROWS

else '0';

o_col_count<=

std_logic_vector( to_unsigned(r_col_Count,o_Col_Count 'length));

o_Row_Count <=

std_logic_vector(to_unsigned(r_Row_count,o_Row_Count' length));

end architecture R T L;