Question

Compare ISA’s of MIPS (MIPS32) and ARM (v7) by instruction <Class.sub.instr>:  ex. <ALU.add>.  

what are the missing and extra instructions.

Answer 1

Answer :-

MIPS and ARM both are from the same family of instruction set but a number of differences can be identified between them.MIPS and ARM are two ISA instruction set architecture which are available in all over the world of microprocessors.MIPS and ARM both are based on the reduced instruction set computing and they are in register type.MIPS and ARM both the instruction sets have 32 bit/64 bit which is fixed instruction size.

Differences between MIPS and ARM

1.ARM has a high throughput and a great efficiency than MIPS because ARM processors support 64-bit

2.MIPS architecture supports the implementation of multiple banks of registers but ARM provides only general purpose registers for arithmetic operations.

3.MIPS and ARM are two different instruction set architectures in the family of RISC instruction set.

4.MIPS and ARM both the instruction sets have a fixed and same instruction size, ARM has only 16 registers while MIPS has 32 registers.

5.MIPS has no equivalent instruction to the ARM MOV instruction.

MIPS32 was designed and introduced by MIPS Technologies in 1981. The MIPS instruction set acknowledges 32 general-purpose registers in the register file.
For most processors implementing the MIPS instruction set architecture, each register is 32 bits in size.
Registers are designated using the “$” symbol.
This ISA is based on RISC instruction set architecture and has a fixed encoding system.
Condition registers are used for branching and MDMX, MIPS-3D are used as extensions.
There are three types of MIPS instructions and they are R, I and J.
Every instruction starts with a 6 bit opcode.
In R type instructions, there are three registers, a shift mount field and a function field.
In I type instructions, there are two registers and a 16 bit immediate value.
In J type instructions follow opcode with a 26 bit jump target.
MIPS has 32 integer registers in order to perform arithmetic operations.
Register $0 holds 0 and register $1 is normally reserved for the assembler.
For all practical purposes, three of these registers have special functionality ($0,29,$31).
MIPs architecture is used in making smart phones, super computers, embedded systems such as routers, residential gateways, and video consoles such as Sony PlayStations.
ARM V7

ARM is an instruction set which is often said to be “RISC” but it’s mostly designed to be a pragmatic instruction set, borrowing only the best RISC ideas, never trying to be a “pure” RISC like MIPS or SPARC.
ARM V7which is the main processor in the mbed development board, utilizes the ARMv7-M Thumb instruction set architecture.
This instruction set acknowledges 15 general-purpose registers in the register file.
Registers are denoted using the <Rn> format, where n denotes the register number. Of these 15 registers, 3 registers have special functionality (R13, R14, R15).
Also, registers R0-R4 (scratch registers) are used for parameter passing and are saved between subroutines.
All registers are 32-bits in size.
ARM processors accounted for approximately 90% of all embedded 32-bit RISC processors and were used extensively in consumer electronics, including personal digital assistants (PDAs), tablets, mobile phones, digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers.
Core Differences

MIPS has more registers and ARM has more addressing modes. There is a similar core of instruction sets for arithmetic-logical and data transfer instructions for MIPS and ARM.
Unlike MIPS, ARM does not reserve a register to contain 0.
Although MIPS has just three simple data addressing modes, ARM has nine.
MIPS uses the contents of registers to evaluate conditional branches. ARM uses the traditional four condition code bits stored in the program status word: negative, zero, carry, and overflow. They can be set on any arithmetic or logical instruction; unlike earlier architectures, this setting is optional on each instruction. An explicit option leads to fewer problems in a pipelined implementation. ARM uses conditional branches to test condition codes to determine all possible unsigned and signed relations