Suppose you are designing a 32-bit sequential ALU. ALU output (HI & LO) is 0 for...
Suppose you are designing a 32-bit sequential ALU. ALU output (HI & LO) is 0 for NoOP operation code. How many 1-bit 11x1 multiplexers do you need to implement the 'result' and 'done' selection for the output fo this ALU?
Homework Answers
By constructing a 1-bit ALU and then create the desired 32-bit ALU by connecting 32 1-bit ALUs.A 1-bit ALU can be constructed using a full-adder, two multiplexors and a few gates. The two 1-bit data inputs are named a and b, and the 1-bit output is named Result. This ALU can perform addition, subtraction, AND, OR on the two data inputs according to an operation code supplied to the ALU. The two-bit control input named Operation partially specifies the operation code.
A 1-bit ALU.
Operation Binvert CarryIn Result Function
00
0
X
a AND b Logical AND
01
0
X
a OR b Logical
OR
10
0
0
a +
b
Addition
10
1
1
a -
b
Subtraction
11
1
1
Less
Sets on less than
X means don't care, + means arithmetic addition, and - means arithmetic subtraction. The four-input multiplexor on the right has its 2-bit select input connected to the Operation line. The output of this multiplexer is the 1-bit output of the ALU named Result. Recall that subtracting b from a is the same as adding the 2's complement of b to a. The two-input multiplexor on the left selects b or its inverted value, depending on the 1-bit select input named Binvert. This input is set to 0 for addition, AND, and OR, and set to 1 for subtraction. The CarryIn input is set to 0 for addition and set to 1 for subtraction.
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Suppose you are designing a 32-bit sequential ALU. ALU output
(HI & LO) is 0 for...
1. Assuming that the ALU has a 6-bit control word, how many different operations can it...
1. Assuming that the ALU has a 6-bit control word, how many different operations can it perform? 2. Consider the ALU shown on slide 9 of Lecture 16. Calculate the result for each operation specified in Table 1. Assume that A 1101 and B 0111. Specify the operation performed, the resut, and the value of each status bit 3 Write the VHDL code to describe an ALU that performs four operations: AND, OR, NOT, and Addition. Use a with-select-when statement....
PROBLEM STATEMENT The mini-calculator will use a small ALU to perform arithmetic operations on two 4-bit values which are set using switches. The ALU operations described below are implemented with a...
PROBLEM STATEMENT The mini-calculator will use a small ALU to perform arithmetic operations on two 4-bit values which are set using switches. The ALU operations described below are implemented with an Adder/Subtractor component. A pushbutton input allows the current arithmetic result to be saved. An upgraded mini-calculator allows the saved value to be used in place of B as one of the operands. The small ALU that you will design will use the 4-bit adder myadder4 to do several possible...
6. In this problem, you are to implement a 3-bit ALU which performs the following 4 operations on 3-bit operands A and B and generates the result F and the overflow status OV: (a) op(1:0) 00: A A...
6. In this problem, you are to implement a 3-bit ALU which performs the following 4 operations on 3-bit operands A and B and generates the result F and the overflow status OV: (a) op(1:0) 00: A AND B (b) op(1:0)#: 01 : A OR B. (c)op(1:0),# 10: A +13. (d) 01, (1 : 0) t# 11 : A B, For arithmetic operations, assume that A and B are two's complement integers, e.g.. 0112 3, n and 1002 ten The...
FIRST ACTIVITY: (100/100) . SIMPLE 4-BIT ARITHMETIC LOGIC UNIT (ALU): This circuit selects between arithmetic (absolute...
FIRST ACTIVITY: (100/100) . SIMPLE 4-BIT ARITHMETIC LOGIC UNIT (ALU): This circuit selects between arithmetic (absolute value, addition) and logical (XOR, AND) operations. Only one result (hexadecimal value) can be shown on the 7-segment display This is selected by the input sel (1..0) B A-BI A+B A xnor B A nand B Input EN: If EN-1result appears on the 7 segment display. If EN=0 → all LEDs in the 7 segment display are off Arithmetic operations: The 4-bit inputs A...
computer architecture The sum of the two 32 bit integers may not be representable in 32 bits. In this case, we say that an overflow has occurred. Write MIPS instructions that adds two numbers stor...
computer architecture
The sum of the two 32 bit integers may not be representable in 32 bits. In this case, we say that an overflow has occurred. Write MIPS instructions that adds two numbers stored in registers Ss1 and Ss2, stores the sum in register $s3, and sets register Sto to 1 if an overflow occurs and to 0 otherwise. 5. (16pts) 6. Show the IEEE 754 binary representation of the number -7.425 in a single and double 7. If...
1) We would like to design a bus system for 32 registers of 16 bits each....
1) We would like to design a bus system for 32 registers of 16 bits each. How many multiplexers are needed for the design? Select one: 5 16 1 4 32 2) The basic computer can be interrupted while another interrupt is being serviced. Select one: True False 3) If the Opcode bits of an instruction is 111, then the basic computer instruction type is either memory-reference or input-output. Select one: True False 4) The content of AC in the...
You know that to multiply a binary integer by 16, all you have to do is...
You know that to multiply a binary integer by 16, all you have to do is shift the value over by 4 bit positions -- which in hardware can literally be done without a function unit simply by connecting bus wires such that bit k goes to position k+4 and positions 0-3 are connected to ground. Well, it's harder to multiply by 15. However, by using Booth's algorithm, a single 32-bit add/subtract ALU is sufficient to implement multiply of a...
2. (15 pts) For the following control signals, C2C1 and C5C4 are used to select source...
2. (15 pts) For the following control signals, C2C1 and C5C4 are used to select source register R[0]-R[3], C3 and C6 is used for Din selection. IfCg = 1, MUX 1 output is Din- If C6-1, MUX2 output is Din- CB, C7 are used for the 2 bit binary decoder to select destination register. C11C1nco are used for ALU selection, and the details are listed in the following table Contro0 000 001 011 100 101 110 Si Operation AB A+BA*BA-B...
Design a sequential system that has one synchronous input bit stream x and one output z, with the following functionality and also follows the design constrains. Design Specifications: Design a sequen...
Design a sequential system
that has one synchronous input bit stream x and one output z, with
the following functionality and also follows the design
constrains.
Design Specifications: Design a sequential system that has one synchronous input bit stream X and one output Z, with the following functionality 1) We look at every fourth-input-bit, while the other input bits are "don't cares". when three "consecutives" fourth-bits form the sequences 110 or 000 the system should output Z = 1, meaning...
Design a circuit that can be built using and, or and invertor gates that will output...
Design a circuit that can be built using and, or and invertor gates that will output a High (1) whenever the 4-bit hexadecimal input is an odd number from 0-9 Hint: You need to ask yourself, how many combinations do I have? How many I am using from them? What should you do with the rest? Minimize the design. Then implement it using Vivado
1. Assuming that the ALU has a 6-bit control word, how many different operations can it perform? 2. Consider the ALU shown on slide 9 of Lecture 16. Calculate the result for each operation specified in Table 1. Assume that A 1101 and B 0111. Specify the operation performed, the resut, and the value of each status bit 3 Write the VHDL code to describe an ALU that performs four operations: AND, OR, NOT, and Addition. Use a with-select-when statement....
PROBLEM STATEMENT The mini-calculator will use a small ALU to perform arithmetic operations on two 4-bit values which are set using switches. The ALU operations described below are implemented with an Adder/Subtractor component. A pushbutton input allows the current arithmetic result to be saved. An upgraded mini-calculator allows the saved value to be used in place of B as one of the operands. The small ALU that you will design will use the 4-bit adder myadder4 to do several possible...
6. In this problem, you are to implement a 3-bit ALU which performs the following 4 operations on 3-bit operands A and B and generates the result F and the overflow status OV: (a) op(1:0) 00: A AND B (b) op(1:0)#: 01 : A OR B. (c)op(1:0),# 10: A +13. (d) 01, (1 : 0) t# 11 : A B, For arithmetic operations, assume that A and B are two's complement integers, e.g.. 0112 3, n and 1002 ten The...
FIRST ACTIVITY: (100/100) . SIMPLE 4-BIT ARITHMETIC LOGIC UNIT (ALU): This circuit selects between arithmetic (absolute value, addition) and logical (XOR, AND) operations. Only one result (hexadecimal value) can be shown on the 7-segment display This is selected by the input sel (1..0) B A-BI A+B A xnor B A nand B Input EN: If EN-1result appears on the 7 segment display. If EN=0 → all LEDs in the 7 segment display are off Arithmetic operations: The 4-bit inputs A...
computer architecture
The sum of the two 32 bit integers may not be representable in 32 bits. In this case, we say that an overflow has occurred. Write MIPS instructions that adds two numbers stored in registers Ss1 and Ss2, stores the sum in register $s3, and sets register Sto to 1 if an overflow occurs and to 0 otherwise. 5. (16pts) 6. Show the IEEE 754 binary representation of the number -7.425 in a single and double 7. If...
2. (15 pts) For the following control signals, C2C1 and C5C4 are used to select source register R[0]-R[3], C3 and C6 is used for Din selection. IfCg = 1, MUX 1 output is Din- If C6-1, MUX2 output is Din- CB, C7 are used for the 2 bit binary decoder to select destination register. C11C1nco are used for ALU selection, and the details are listed in the following table Contro0 000 001 011 100 101 110 Si Operation AB A+BA*BA-B...
Design a sequential system
that has one synchronous input bit stream x and one output z, with
the following functionality and also follows the design
constrains.
Design Specifications: Design a sequential system that has one synchronous input bit stream X and one output Z, with the following functionality 1) We look at every fourth-input-bit, while the other input bits are "don't cares". when three "consecutives" fourth-bits form the sequences 110 or 000 the system should output Z = 1, meaning...
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