The following comprise an actual 2 μm p-well CMOS
process flow with poly-to-poly
capacitors. No details are spared in this flow; even equipment
names are given, as are
diagnostic steps used to verify each step. LPCVD furnace program
names are also given.
These details are included to present a more realistic situation.
In doing this problem, you
must sift through the extraneous information and concentrate on the
recipe information
(i.e., temperatures, times, implant doses, etc…).
Answer the following questions based on the following
process.
(a) Draw a qualitative cross-section corresponding to the line A-A’
in the layout
below. Identify layers and try to draw thicknesses to scale. (You
should
distinguish between CVD oxides and thermally grown oxides-i.e.,
label them).
Note that although capacitors are not used in this layout, you may
need to account
for the process steps involved with poly-to-poly capacitor
formation to get a
sufficiently accurate cross-section. Note that mask layers are
identified in the
drawing below. ‘df’= dark field (i.e. box shows where an opening in
the PR will
be) and ‘cf’= clear field (i.e., box shows the portion to be
covered by PR).
(b) What is the gate oxide thickness tox?
(c) What is the depth Xjn of the NMOS n+ S/D junctions at the end
of process?
(d) What is the depth Xjp of the PMOS p+ S/D junctions at the end
of process?
(e) What is the gate overlap capacitance (i) for NMOS devices? (ii)
for PMOS
devices?
(f) What is the threshold voltage Vtn for the NMOS devices of this
process for zero
source to bulk voltage, VSB=0 V? Assume that the fixed charge at
the gate oxide
is negligible. (Note that this may or may not be a good assumption.
Don’t be
surprised if you get a strange value for Vtn).
(g) What is the threshold voltage Vtp for the PMOS devices of this
process for zero
source to bulk voltage, VSB=0 V? Assume that the fixed charge at
the gate oxide
is negligible. (Note that this may or may not be a good assumption.
Don’t be
surprised if you get a strange value for Vtp).
(h) Calculate k’n=μnCox and k’p=μpCox for this process.
(i) Assuming the p-well is tied to ground, what is the minimum
value of voltage on a
metal line over the field region in the p-well that would invert
the p-well surface?
The following comprise an actual 2 μm p-well CMOS process flow with poly-to-poly capacitors. No details...
CMOS VLSI DESIGN, Please attempt all the
objective type questions.CMOS
Question 1: Select the single correct answer [2 marks each] Which of the following statements is true for a MOSFET switch (input is gate node)? A) nMOS is off with logic I' at input B) nMOS is on with logic '1' at input C) pMOS is on with logic '1' at input' D) pMOS is off with logic '0' at input Which of the following CMOS logic circuits will contain...