Question

Write a parametric Verilog module for each the following designs: (a) Instruction Memory. (b)Data Memory, Your Instruction Memory and Data Memory should be able to read MIPS instructions or data from either a .txt or a .mem file.

Answer 1

(a) Parametric Verilog module for Instruction Memory

//   Imem:   The Instruction Memory module
//   Parameter List:
//       clk:       the memory clock (input)
//       address:   the instruction address (input)
//       instruction:   the instruction (output)
//
//   Date:   12-02-2020
//
//

module Imem (clk, address, instruction);

input       clk;
input   [7:0]   address;
output   [7:0]   instruction;

reg   [7:0]   instruction;

//   memAddr is an address register in the memory side.
reg   [7:0]   memAddr;
reg   [7:0]   Imem[0:512];

   //   Definition of the latency to latch the address and
   //   read the memory.
parameter   addressLatch = 10, memDelay = 70;

   //   The I-Memory is initially loaded
initial
   $readmemb ("Imem.data", Imem);

   //   I-mem is read in every cycle.
   //   A read signal could be added if neccessary.
always @(posedge clk) begin
   #addressLatch   memAddr = address;
   #memDelay   instruction = Imem[memAddr];
end

endmodule

(b) Parametric Verilog module for Data Memory

module data_memory (
input wire [31:0] addr, // Memory Address
input wire [31:0] write_data, // Memory Address Contents
input wire memwrite, memread,
input wire clk, // All synchronous elements, including memories, should have a clock signal
output reg [31:0] read_data // Output of Memory Address Contents
);

reg [31:0] MEMO[0:255]; // 256 words of 32-bit memory

integer i;

initial begin
read_data <= 0;
for (i = 0; i < 256; i = i + 1) begin
MEMO[i] = i;
end
end

always @(posedge clk) begin
if (memwrite == 1'b1) begin
MEMO[addr] <= write_data;
end
if (memread == 1'b1) begin
read_data <= MEMO[addr];
end
end

endmodule